JPS5853791B2 - character recognition device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character recognition device, in particular a character recognition device for e.g.
Dictionary information that can be collated for various character types such as alphabetic characters, alphabetic symbols, alphanumeric characters, alphanumeric symbols, kana, kana numeric characters, alphanumeric kana, etc. is mixed and stored in the dictionary memory, and The present invention relates to a character recognition device that is capable of extracting dictionary information that can be checked in accordance with character types at high speed.

Dictionary information prepared in a dictionary memory in conventional character recognition devices has been created and managed for each type of character to be recognized.

That is, when recognizing alphanumeric characters, a dedicated dictionary memory for collating alphanumeric characters has been used, and when recognizing alphanumeric kana characters, a dedicated dictionary memory for alphanumeric kana characters has been used.

However, as the number of recognizable characters increases to include numbers, numeric symbols, alphabetic characters, alphanumeric symbols, alphanumeric characters, alphanumeric symbols, kana, kana numeric characters, alphanumeric kana... Memory management becomes complicated, and a lot of common dictionary information is included between dedicated dictionary memories, which becomes uneconomical in terms of effective use of dictionary memories.

That is, when dictionary information stored in the dictionary memory, for example, dictionary information corresponding to a modified character, is used as dictionary information for recognition processing corresponding to the numeric mode, for example, it is prepared as corresponding to category "2". , and when used as dictionary information for recognition processing corresponding to the kana mode, a situation arises in which the dictionary information is prepared as corresponding to the category "yu", which makes management complicated.

Taking the above points into consideration, the present invention centralizes the dictionary memory and uses the field read mode when reading a form (whether the characters written on the form are only numbers or alphanumeric characters...
The purpose of the present invention is to enable high-speed extraction of only dictionary information that can be checked from the unified dictionary memory.

Therefore, the character recognition device of the present invention scans the characters on the form in which the recognition target character is written, extracts the features, and extracts the features from the multiple types of characters mixedly stored in the dictionary memory. In a character recognition device that recognizes the recognition target character by comparing it with corresponding dictionary information, the dictionary information includes character types that can be compared with category information and feature information in each dictionary information. a storage means for storing field read mode information configured to describe mode information and indicating the character type described on the form; and character type mode information read from the dictionary memory; Fields stored in the above storage means
A mode collation circuit unit is provided to collate the read mode information, and the mode collation circuit unit checks whether or not the dictionary information can be collated with respect to each piece of dictionary information sequentially read from the dictionary memory. This feature is characterized in that if it is impossible, the next dictionary information is read out without performing the above verification.

This will be explained below with reference to the drawings. FIG. 1 is an explanatory diagram illustrating the prerequisite problem of the present invention, FIG. 2 shows the configuration of an embodiment of the invention, and FIG. 3 shows an embodiment of dictionary information.

As mentioned at the beginning of this specification, as the number of recognizable character types increases, the number of dictionary memories that were conventionally managed for each character type increases, and the amount of dictionary information common between different dictionary memories increases. (Ru.

For this reason, it is desirable to unify dictionary memories that have been developed individually.

Conventionally, as shown in Figure 1, fields and
Depending on the read mode, for example, numeric mode N, numeric symbol mode Ns, alphanumeric mode A, alphanumeric symbol mode A
s, alphanumeric mode AN, alphanumeric symbol mode ANs, kana mode with one digit kana mode NK, alphanumeric kana mode AN
K nine types of dictionary memories are prepared.

When such dictionary memories are unified, as shown in Figure 1 (A) When the field read mode is numeric,
Dictionary mode N, Ns t AN, ANs, NK.

Dictionary information belonging to ANK is available for verification; (B) For numeric symbols, dictionary mode NS, ANs
(C) Similarly, in the case of alphanumeric kana, dictionary mode ANK can be used.

On the other hand, by unifying the dictionary memory as mentioned above,
Dictionary information that previously belonged to the various modes described above is stored in a mixed manner on the dictionary memory.

For this reason, it is necessary to extract only dictionary information that can be collated at high speed in accordance with a given field read mode, and then collate it.

FIG. 2 shows the configuration of an embodiment of the present invention.

Reference numeral 1 in the figure is a dictionary memory in which dictionary information is stored, and reference numeral 2 is a memory address register, which is used for control after one start address (first address of dictionary information) is set as described later. 3 is a next start address register, which is incremented (iNC) by an instruction from the CONTL unit and sequentially reads out the byte unit information in the dictionary's report from the dictionary memory 1. 4 is an adder that calculates the start address; 7 is a selection circuit; 8 is a memory access control circuit; 9 is a clock; 10 is read data.・Register distribution counter,
11 is a read data register distribution instruction decoder, 1
2-0, 12-1, and 122 are read data registers, 13-0 is a mode matching detection circuit constituting the mode matching circuit section according to the present invention, and 13-1 is the mode matching circuit section according to the present invention. The constituent symbol suppress detection circuits include a failure countermeasure set circuit 14, an OR circuit 15, and a field read mode setting register 16.

The dictionary information stored in the dictionary memory 1 is configured as shown in FIG. It is distributed and set from -0 to 12-2.

The above dictionary information is the first #1 byte as shown in Figure 3)
a byte length instruction part (length), and the next #2 byte b the symbol suppression bit information S1. S2, and then the next #3 By) c is kana/alphabetic/numeric dictionary mode information KAN, and pie) d is generally multiple category names, pie) e is MAP of MAP, byte f A maximum of 16 bytes of MAP is prepared in , and a maximum of 128 bytes of dictionary information (stored in a compressed manner) is prepared in byte g.

In the figure, the memory access control unit 8 is omitted for controlling access to the dictionary memory 1 using the map information, and the comparison with feature information extracted from the recognition target character using the feature information is omitted. .

In addition, in the case shown in the figure, in the dictionary mode instruction section in the dictionary information, either mode N, A, AN, NK, or ANK is specified by the information KAN, and mode N or Ns or A or As is specified. , AN or ANs is selected using symbol suppress-bit information S1. Indicated by S2.

The operation shown in FIG. 2 is performed as follows.

That is, (1) Field read mode is given from the form side and set in the field read mode register 16.

The 3 bits in the content correspond to the above information KAN and indicate any of numbers, alphabets, alphanumeric characters, kana, kana numeric characters, alphanumeric kana, and the 2 bits correspond to the above signal suppression bit information. S1. Indicates whether it is a numeric symbol, alphabetical symbol, or alphanumeric symbol that corresponds to S2.

(2) When reading dictionary memory 1, the initial start address (INITIAL START
ADR8) is set in the memory address register 2 via the selection circuit 7 and the adder 4.

Then, the dictionary memory 1 is accessed according to the contents of the register 2.

(3) As a result, the first byte of one dictionary information is read and set in the read data register 12-0 according to an instruction from the decoder 11.

The first byte indicates the byte length of the dictionary memory.

The byte length is supplied to the adder 4, where it is added to the initial start address, and the start address of the next dictionary information is held in the register 3.

(4) Next, the previously set address register 2
The content of is incremented by 1 by an instruction from the control circuit unit 8, and the information of the #2 byte of the dictionary information is read from the dictionary memory 1.

Then, according to an instruction from the decoder 11, it is set in the read data register 12-1.

The information of the #2 byte is suppress bit information S1. as shown in FIG. S2, and the dictionary information is mode N or N.
It indicates whether it is s, A or As, AN or ANs.

(5) As a result, the symbol suppression detection circuit 13-1 operates as follows, for example.

That is, when it is assumed that the field read register 16 instructs recognition of characters including symbols, the read dictionary information does not recognize symbols (mode N,
A, AN), the illustrated signal S1 and/or S2 outputs a logic "1".

(6) Therefore, the OR circuit 15 outputs logic "1",
Next dictionary information read start (N
XT 5TART).

The control circuit unit 8 immediately interrupts the reading of the subsequent bytes regarding the dictionary information and sets the contents of the register 3 to the address.
Set in register 2 and read the first byte of the next dictionary information.

That is, since the dictionary information cannot be compared against characters including symbols, the user immediately reads the next dictionary information.

(7) Suppose that the above signals s1 and/or s2 are logic “1”
”, the control circuit unit 8 next increments the contents of the address register 2 and sets #3 of the dictionary information.
Read byte.

That is, it is set in the IJ-code data register 12-2.

The information in the #3 byte is mode information KA as shown in Figure 3.
N, and the dictionary information is in mode N (or Ns), A(
or As), AN (or ANs), NK,
It indicates which one is ANK.

(8) As a result, mode coincidence detection circuit 13-b sets signal S3 to logic "1" if it contradicts the instruction from field read register 16.

That is, it notifies the control circuit section 8 via the OR circuit 15, interrupts the subsequent collation process for the dictionary information, and reads the next dictionary information.

Note that the above information S1.corresponds to the position of the form. Bit information corresponding to S2 and information KAN is created in advance, and corresponding information is set in the field read mode setting register 16 depending on which position on the form is currently being recognized.

As mentioned above, in the illustrated embodiment, before starting the matching process,
It is checked whether the dictionary information that is currently being read is collated dictionary information or not, and if it is not collated, the next dictionary information is immediately fetched.

The 3 bits that indicate the dictionary mode supplied to the mode-number configuration circuit 13-0 are "OOl" for modes N and Ns, "0 for mode A and As" and "0 for IOJ mode". "100" for mode AN and ANs, "101" for mode NK,
It can be considered that "111" is given in the case of mode ANK.

Also, the 3 bits given from the field read mode are "OOl" for numbers and numerical symbols, j'-010j for alphabetic characters and alphanumeric symbols, and l100 for kana.
It may be assumed that "011" is given for j alphanumeric characters and alphanumeric symbols, "101" is given for kana numeric characters, and "l 11j" is given for alphanumeric kana characters.

Therefore, the mode-number configuration circuit 13-0 can be considered to have a configuration that compares the two inputs in bit correspondence and outputs a logic "1" as the signal S3 when they do not match.

The case of the symbol suppression detection circuit is almost the same, and the two bits indicating the dictionary mode are "01" in the case of mode N;
"10" for mode A, "11" for mode AN
” can be considered as something that can be given.

The failure countermeasure set circuit 14 shown in FIG. 2 is prepared for the following situations.

That is, for example, if dictionary information corresponding to the character "8" always gives an error such as recognizing the character B, the first two bits of the dictionary information are deleted in order to prevent the dictionary information from being used from now on. It may be used to instruct against use.

The fault countermeasure set circuit 14 detects that the above-mentioned prohibited dictionary information has been read out, and immediately enters the next 7-etch of the dictionary information via the OR circuit 15.

As explained above, according to the present invention, it is possible to centralize dictionary memories that were conventionally managed by different sides, and furthermore, when dictionary information in a mode that does not match the matching process is read out, subsequent matching processing is interrupted. Then, the next dictionary information can be immediately fetched, and the overall recognition processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram illustrating the prerequisite problem of the present invention, FIG. 2 shows the configuration of an embodiment of the invention, and FIG. 3 shows an embodiment of dictionary information. In the figure, 1 is a dictionary memory, 2 is a memory address register, 3 is a next start address register, 4 is an adder, 8 is a memory access control circuit section, 12-0 to 1
2-2 are read data registers, 13-0,
13-1 is a mode verification circuit, and 16 is a field/
Represents the read mode setting register.

Claims (1)

[Scope of Claims] 1. A method that corresponds to the result of feature extraction by scanning the characters on the width sheet in which the recognition target character is written and the multiple types of characters stored in a mixed manner in the dictionary memory. In a character recognition device that recognizes the recognition target character by comparing it with a dictionary information, the dictionary information is set in a character type mode in which the dictionary information can be compared together with category information and feature information in each individual dictionary information. a storage means for storing field read mode information that describes the character type written on the form, and the character type mode information read from the dictionary memory; A mode matching circuit section is provided to match the field read mode information stored in the storage means, and the mode matching circuit section can match each dictionary information sequentially read from the dictionary memory. 1. A character recognition device characterized in that the character recognition device checks whether or not the matching is possible, and reads the next dictionary information without performing the matching if the matching is impossible. 2. The character recognition device according to claim 1, wherein the character type mode includes at least a numeric mode, an alphanumeric mode, an alphanumeric mode, a kana mode, a numeric kana mode, and an alphanumeric kana mode. 3. The character recognition device according to claim 2, wherein the character type mode includes a numeric symbol mode, an alphanumeric symbol mode, and an alphanumeric symbol mode.