JPS5853811B2 - Multi-frequency signal receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-frequency signal receiving device for signal identification, which is used, for example, in a multi-frequency receiving system (MF receiving system).

When receiving multi-frequency signals used for inter-office connections in telephone exchange systems, it is necessary to accurately identify incoming input signals, and it is necessary to prevent malfunctions due to noise, etc. In multi-frequency reception systems. Usually, two types of frequencies are expected to arrive.

For example, 700,900,1100°1300.15
It is a combination of any two of 0.00.1700Hz.

Conventionally, as a receiving method, a pulse train corresponding to the input frequency is integrated, and a timer is used to prevent output from being output for a certain period of time after the arrival of the input signal, but this method is completely ineffective against noise other than the received signal. It was not possible to prevent malfunctions.

FIG. 1 is an example of a multi-frequency signal receiving apparatus showing a conventional reception method, and FIG. 2 is a time chart of the signals in FIG. 1.

The above problem will be explained below with reference to FIGS. 1 and 2.

In FIG. 1, 1 is an input terminal, 2 is a band p-wave device, 3 is a detection circuit, 5 is a gate, 6 is an output terminal, and 4 is a timer.

Here, when the noise waveform S1 shown in FIG. 2 is input to the cutting terminal, the response waveform S2 shown in FIG. 2 is obtained by the bandpass filter 2.

After the detection circuit 3 detects the output of the bandpass filter using an appropriate threshold value, it is integrated and waveform shaped to obtain the output waveform S3 in FIG. 2.

On the other hand, the timer 4 starts counting immediately after the signal is applied to the input terminal 1, and after a certain period of time (TG) has elapsed, the output waveform S4 shown in FIG. 2 is obtained.

As a result, if the output terminal 6 receives the output of the timer 4 and the output of the detection circuit 3, the output waveform S5 shown in FIG. 2 will be output.

Note that 81 to S5 in FIG. 2 are, for example, 81 to S5 in FIG.
The waveform is shown when noise is detected corresponding to , and the part indicated by a dotted line shows the case when an original normal frequency signal is detected.

In this manner, in the conventional method, noise within a certain time period (TG) can be removed, but noise longer than that is output to the subsequent circuit as a normal signal.

Furthermore, if three or more frequency signals are mistakenly detected at the same time, they will be output in the same way.

In this way, complete protection cannot be provided against noise input.

In view of the above-mentioned problems, an object of the present invention is to prevent malfunctions in multi-frequency signal reception by providing means for confirming the continuation of the arrival of input signals meeting predetermined conditions in a multi-frequency signal receiving device. , to accurately receive multi-frequency signals.

In the present invention, in a multi-frequency signal receiving device that receives m frequencies out of n frequencies, the output of a flip-flop circuit connected for each frequency is connected to an output gate, and the output of the flip-flop circuit is connected to an output gate of the flip-flop circuit. a first signal presence detection logic circuit that operates only when there are m or more input signals among the n input lines, and operates only when there are m or less input signals among the n input lines; Second
a signal presence detection logic circuit, and an m/n check circuit consisting of an AND gate, the output of the first signal presence detection logic circuit being connected to a first input terminal of the AND gate and a first input terminal of the inhibition gate. The output of the second signal presence detection logic circuit is connected to the second input terminal of the AND gate, and the output of the AND gate is connected to the second input terminal of the inhibit gate and the output gate of the inhibit gate via a timer. The output of the inhibit gate is connected to the reset input of the flip-flop circuit, and the pulse train is integrated at the output of the AND gate to perform counting for a certain period of time. At the same time, the resetting of the flip-flop circuit is stopped by the action of the inhibiting gate, and an output signal is sent from the output gate to identify the arrival of a received signal. Ru.

According to the embodiment of the present invention, the predetermined frequency reception state m/n in the flip-flop of the multi-frequency signal receiving device is checked using a logic circuit, and the flip-flop is repeatedly set and reset to confirm that the signal is a normal signal. By doing so, malfunctions can be eliminated.

That is, an excellent effect can be obtained in that the influence of noise can be reliably eliminated in the reception of multi-frequency signals.

Therefore, the receiving operation in the multi-frequency signal receiving method can be performed accurately.

Referring to FIG. 3, the present invention will be described in detail.

In this embodiment, a case where n is 6 and m is 2 will be described, that is, two frequencies out of six frequencies are received.

A received @ signal enters input terminal 1, and the band-width transducer group 11.12
．． ...16, each frequency is extracted and the detector group 2L22. ... 26 to the flip-flop group 31,
32. ...36 is supplied.

The output of the operated flip-flop is routed to a first signal presence detection logic circuit 41 and a second signal presence detection logic circuit 42, where the logic circuit 41 connects two of the six input lines.
Similarly, the logic circuit 42 operates only when there are two or less input signals out of six.

The output of the logic circuit 41 is inputted to the reset terminals of the flip-flops 31, 32, . . . , 36 via the inhibit gate 53 to reset the flip-flops.

In this case, flip-flops 31, 32 . The timing of supplying the reset signal to .

The detector outputs a rectangular wave pulse consisting of a high level part and a low level part, and when the high level part is input, the flip-flop is set, and based on the signal output of the flip 70 tube based on this, as described above. When the flip-flop is reset, if the output of the detector is still at a high level, the above operation is repeated and the flip-flop is reset again, thus changing the output of the detector from a high level to a low level. Setting and resetting are repeated until a change occurs.

Here, the reason why the flip-flop group is reset when two or more of the six inputs is received is that the multi-frequency In the signal receiver, since the bandpass filter groups 11 to 12 output an excessive response when the input signal is low, the flip-flops 31 to 36 must operate by 2/6 or more, and noise is mixed into the input signal. Even in this case, the flip-flops 31 to 36 operate at 2/6 or more.

In the field of multi-frequency reception systems, experience shows that when noise is input manually as an input signal, in the case of n6, m = 2 in Fig. 3, 3 of the detectors 21, 22°...26
More than one are known to operate and produce high level outputs.

(Note that similar circumstances exist in cases other than the case where n = 6 and m = 2.

) Therefore, when noise is mixed into the input signal, the flip-flops 31 to 36 operate at 2/6 or more.

Next, the detector group 21, 22 . . . . The flip-flop is set again by the output of 26, and the flip-flop is set in accordance with the operation of the detector group.

In this way, in the case of "two or more out of six", the flip-flops are repeatedly set and reset as long as there is an output from the detector, and as a result, a pulse train is generated.

In this state, when the state of the outputs of the flip-flops 31 to 36 is exactly "only 2 out of 6", the logic circuits 41 and 42 and the AND gate 51 act to cause the AND gate 51 to also generate a pulse train at its output. .

A timer 52 is connected to the output of the AND gate 51, which integrates the pulse train to count a certain period of time, and at the same time as the counting ends, the inhibit gate 53 stops resetting the flip-flop, thereby maintaining the holding state of the flip-flop. Continue and output gates 61, 62 . ---66 is opened, and the output terminals 71, 72 . ...Sends the output to 76.

The fixed time of this timer 52 is empirically determined to be the time required to completely identify whether the input signal is an original signal or noise in a multi-frequency signal receiving system to which the device shown in FIG. 3 is applied. Selected as

That is, the timer 52 monitors by counting the continuation of two normal frequencies for a certain period of time, and if it is "2 or more out of 6" and continues for the certain period of time, the reception is normal. Even if the number is 2 out of 16, if it does not continue for the certain period of time, it is determined that there is a noise component.

If it is determined that there is a noise component, the timer 52 is in the initial state.

If only noise is input, the timer 52 does not operate because "two or more of the six flip-flops" described above operate.

As a result, nothing is output to the output terminal.

As shown in FIG. 3, logic circuits 41 and 42 are required in the device shown in FIG. 3, and the flip-flop is reset by logic circuit 41, which operates only when input signals are present in "two or more of six". A timer, a deterrent gate, and an AND logic output of the output of the logic circuit 42 and the output of the logic circuit 41, which operate only when input signals are present in "two or less of six". Flip-flop and output gate operations are performed.

As explained above, in the apparatus shown in FIG.
Prepare to reset the flip-flop circuits (31 to 36) (that is, make one input of the gate 53 the second), and start the timer until reception of m/n or less is made by the second signal presence detection circuit. Therefore, flip-flops (31~
36) By setting the IJ, the noise part (as shown in Fig. 2) is removed, and the flip-flops (m out of 31 to 36) are removed only when m/n is detected.
The signals held at the gates are outputted through gates 61-66.

Therefore, a predetermined number of multifrequency signals that are not affected by noise can be reliably received at the receiver of the multifrequency signal.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional multi-frequency signal receiving device, FIG. 2 is a diagram showing a time chart of the device shown in FIG. 1, and FIG. 3 is a multi-frequency signal receiving device as an embodiment of the present invention. FIG. 2 is a diagram showing the configuration of the device. 1...Input terminal, 11.12. ...16...
...Saibuki, 21.22.・・・26・・・・・・
Detector, 31, 32° 36...Flip-flop, 41, 42...Logic circuit, 51...
...and gate, 52...timer, 53...
... Deterrence gate, 61, 62. ...66...
...output gate, 71°72, ...76...output terminal.

Claims (1)

[Claims] 1. In a multi-frequency signal receiving device that receives m frequencies out of n frequencies, the output of a flip-flop circuit connected for each frequency is connected to output gain-1, and the output of the flip-flop circuit connected to the output of the flip-flop circuit is a first signal presence detection logic circuit that operates only when m or more input signals exist among the n input lines; and a first signal presence detection logic circuit that operates only when m or less input signals exist among the n input lines. an m/n check circuit consisting of two signal presence detection logic circuits and an AND gate, the output of the first signal presence detection logic circuit being connected to the first input terminal of the AND gate and the first input terminal of the inhibition gate. terminal, the output of the second signal presence detection logic circuit is connected to a second input terminal of the AND gate, and the output of the AND gate is connected via a timer to the second input terminal of the inhibit gate and the output gate. The output of the inhibit gate is connected to the reset input of the flip-flop circuit, and the pulse train at the output of the AND gate is integrated to perform counting for a certain period of time, and the counting ends. At the same time, the resetting of the flip-flop circuit is stopped by the action of the inhibiting gate, an output signal is sent out from the output gate, and arrival of a received signal is identified. .