JPS5853870B2 - Decca receiver phase comparison method - Google Patents
Decca receiver phase comparison methodInfo
- Publication number
- JPS5853870B2 JPS5853870B2 JP15122979A JP15122979A JPS5853870B2 JP S5853870 B2 JPS5853870 B2 JP S5853870B2 JP 15122979 A JP15122979 A JP 15122979A JP 15122979 A JP15122979 A JP 15122979A JP S5853870 B2 JPS5853870 B2 JP S5853870B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- signal
- voltage controlled
- phase
- phase difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S1/00—Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmitters; Receivers co-operating therewith
- G01S1/02—Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmitters; Receivers co-operating therewith using radio waves
- G01S1/08—Systems for determining direction or position line
- G01S1/20—Systems for determining direction or position line using a comparison of transit time of synchronised signals transmitted from non-directional antennas or antenna systems spaced apart, i.e. path-difference systems
- G01S1/30—Systems for determining direction or position line using a comparison of transit time of synchronised signals transmitted from non-directional antennas or antenna systems spaced apart, i.e. path-difference systems the synchronised signals being continuous waves or intermittent trains of continuous waves, the intermittency not being for the purpose of determining direction or position line and the transit times being compared by measuring the phase difference
- G01S1/306—Analogous systems in which frequency-related signals (harmonics) are compared in phase, e.g. DECCA systems
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Position Fixing By Use Of Radio Waves (AREA)
Description
【発明の詳細な説明】
本発明は逓倍器を必要としない改良されたデツカ受信装
置の位相比較方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved phase comparison method for a digital receiver that does not require a multiplier.
デツカ航法システムは、送信周波数が一定の基本周波数
fに対して互に高調波関係にある主局6fと2または3
の従局5f、8fおよび9fの電波を、船舶、航空機等
の移動体に3いて受信し、主従両局信号間の位相差を測
定して等位相差双曲線を求め、このようにして求められ
た2または3の双曲線の交点から、移動体の位置を決定
する無線航法方式である。The Detsuka navigation system uses main stations 6f and 2 or 3 whose transmission frequencies are in a harmonic relationship with respect to a constant fundamental frequency f.
Radio waves from slave stations 5f, 8f, and 9f are received by a mobile object such as a ship or an aircraft, and the phase difference between the signals of the main and slave stations is measured to obtain an equal phase difference hyperbola. This is a radio navigation system that determines the position of a moving object from the intersection of two or three hyperbolas.
移動体のデツカ受信装置にかいては、各局の高調波関係
にあるが異なる周波数の送信信号の位相差を求めるため
、受信増幅の後、受信信号をそれぞれの受信信号の最小
公倍数の周波数に逓倍して、同一周波数の信号になるよ
うに変換を行なってから、位相弁別器によって位相差を
求める。In mobile DETSUKA receivers, in order to find the phase difference between transmit signals of different frequencies that are harmonic related to each station, after receiving amplification, the received signals are multiplied to the least common multiple frequency of each received signal. Then, the signals are converted to have the same frequency, and then the phase difference is determined by a phase discriminator.
例えば主局の周波数が6fであり、従局の周波数が5f
であった場合、最小公倍数の周波数3Ofになるように
、それぞれ5逓倍または6逓倍を行なって、得られた信
号について位相比較を行なって位相差を求める。For example, the frequency of the main station is 6f and the frequency of the slave station is 5f.
If so, the signals are multiplied by 5 or 6, respectively, so that the frequency becomes the least common multiple of 3Of, and the phases of the obtained signals are compared to determine the phase difference.
このように従来のデツカ装置にち・いて一般に用いられ
てきた位相比較方式は、−ヒ述のごとき最小公倍数の周
波数斗で受信信号を逓倍して位相比較する方式であった
。As described above, the phase comparison method that has been generally used in conventional deck equipment is a method in which the received signal is multiplied by the least common multiple frequency and the phases are compared.
第1図は従来のデツカ受信装置にむける位相比較方式の
構成を示すブロック図である。FIG. 1 is a block diagram showing the configuration of a phase comparison method for a conventional digital receiver.
同図において、1は受信空中線、2.3は高周波増幅器
、4.5は混合回路、6は局発原振回路、7はM分周む
よびパルス整形回路、8.9は逓倍器、10.11は中
間周波増幅器、12.13は位相差検出回路、14.1
5は電圧制御発振器、16.17は低域フィルタ、18
.19は逓倍器、20は位相差検出回路、21は位相差
指示器である。In the figure, 1 is a receiving antenna, 2.3 is a high frequency amplifier, 4.5 is a mixing circuit, 6 is a local oscillator circuit, 7 is an M dividing and pulse shaping circuit, 8.9 is a multiplier, and 10 .11 is an intermediate frequency amplifier, 12.13 is a phase difference detection circuit, 14.1
5 is a voltage controlled oscillator, 16.17 is a low pass filter, 18
.. 19 is a multiplier, 20 is a phase difference detection circuit, and 21 is a phase difference indicator.
第1図に釦いて空中線1の受信入力は高周波増幅器2.
3に加えられる。As shown in FIG. 1, the reception input of the antenna 1 is connected to the high frequency amplifier 2.
Added to 3.
高周波増幅器2.3はそれぞれ例えば主局の信号mf(
mは逓倍次数、m=6)、従局の周波数nf(nは逓倍
次数、n=5,8,9)を選択的に増幅してそれぞれ混
合器4,5に加える。The high frequency amplifiers 2.3 each have, for example, the main station signal mf(
m is the multiplication order, m=6), and the frequency nf of the slave station (n is the multiplication order, n=5, 8, 9) is selectively amplified and applied to mixers 4 and 5, respectively.
ここでfは受信波の基本周波数(If二14 KHz
)である。Here, f is the fundamental frequency of the received wave (If214 KHz
).
局発原振回路6は11(Aは局発信号の基本周波数、M
は逓倍次数)の周波数の信号を発生する。The local oscillation source circuit 6 is 11 (A is the fundamental frequency of the local oscillation signal, M
is a multiplication order).
M分周器よびパルス整形回路7は信号MAをM分周しパ
ルス整形して周波数Aのパルス信号を発生する。The M frequency divider and pulse shaping circuit 7 divides the signal MA by M and pulse shapes the signal MA to generate a pulse signal of frequency A.
逓倍回路8,9はそれぞれパルス信号Aをm逓倍、n逓
倍してそれぞれmA、nJの周波数の信号を発生し、そ
れぞれ混合器4.5に加える。Multiplier circuits 8 and 9 multiply the pulse signal A by m and n, respectively, to generate signals with frequencies of mA and nJ, respectively, and apply them to mixer 4.5.
混合器4.5はそれぞれ差周波数の信号mF=mJ−m
f、nF=nJ−nfをとり出してそれぞれ中間周波増
幅器10.11に加える。The mixers 4.5 each receive a signal of difference frequency mF=mJ−m
f, nF=nJ-nf are taken out and applied to intermediate frequency amplifiers 10 and 11, respectively.
ここでFは中間周波数の基本周波数(従来方式では1F
=16 KHz )であり、F=A−fの関係にある。Here, F is the fundamental frequency of the intermediate frequency (1F in the conventional method)
= 16 KHz), and there is a relationship of F=A−f.
中間周波増幅器10.11はそれぞれ中間周波数信号m
F、nFを増幅して、それぞれ位相差検出回路12.1
3に加える。The intermediate frequency amplifiers 10 and 11 each receive an intermediate frequency signal m
F and nF are amplified and each phase difference detection circuit 12.1
Add to 3.
位相差検出回路12.13はそれぞれ中間周波数信号m
F、nFを、それぞれ電圧制御発振器14の発生した周
波数mFの信号釦よび電圧制御発振器150発生した周
波数nFの信号と位相比較してそれぞれの位相差に対応
した信号を発生する。The phase difference detection circuits 12 and 13 each receive an intermediate frequency signal m
F and nF are compared in phase with a signal button having a frequency mF generated by the voltage controlled oscillator 14 and a signal having a frequency nF generated by the voltage controlled oscillator 150, respectively, to generate signals corresponding to the respective phase differences.
位相差検出回路12.13のそれぞれの位相差出力信号
はそれぞれ低域フィルタ16.17を経て平滑化された
のち、それぞれ電圧制御発振器14.15に帰還され、
それぞれの位相差出力が零に近づくように発振周波数の
制御が行われる。The phase difference output signals of the phase difference detection circuits 12.13 are smoothed through low-pass filters 16.17, and then fed back to the voltage controlled oscillators 14.15, respectively.
The oscillation frequency is controlled so that each phase difference output approaches zero.
このようにして電圧制御発振器14.15のそれぞれの
出力mF、nFはそれぞれ中間周波数信号mF、nFに
位相同期される。In this way, the respective outputs mF, nF of the voltage controlled oscillators 14.15 are phase-locked to the intermediate frequency signals mF, nF, respectively.
位相差検出回路12、電圧制御発振器14釦よび低域フ
ィルタ16、位相差検出回路13、電圧制御発振器15
および低域フィルタ17はそれぞれ狭帯域の可変周波数
能動フィルタ(トラッキングループフィルタ)として動
作している。Phase difference detection circuit 12, voltage controlled oscillator 14 button and low pass filter 16, phase difference detection circuit 13, voltage controlled oscillator 15
and the low-pass filter 17 each operate as a narrow band variable frequency active filter (tracking loop filter).
電圧制御発振器14.15の出力信号mF、nFはそれ
ぞれ逓倍器18.19にむいてp逓倍またはq逓倍され
て、それぞれmpF、nqFの周波数を有する信号を発
生する。The output signals mF and nF of the voltage controlled oscillator 14.15 are multiplied by p or q, respectively, to a multiplier 18.19 to generate signals having frequencies of mpF and nqF, respectively.
ここで基本周波数Fに対する倍率mp−nqになるよう
に選ばれている。Here, the multiplication factor mp-nq with respect to the fundamental frequency F is selected.
信号mpF、nqFは位相差検出回路20において位相
比較されて位相差に応じた出力を発生し、位相差指示器
21はこれを指示する。The signals mpF and nqF are phase-compared in a phase difference detection circuit 20 to generate an output according to the phase difference, and a phase difference indicator 21 indicates this.
第2図は第1図に示された従来方式に釦ける各部信号の
周波数と位相関係を示す波形図である。FIG. 2 is a waveform diagram showing the frequency and phase relationship of each part signal of the conventional method shown in FIG. 1.
同図にトいてす、dはそれぞれ電圧制御発振器14.1
5の出力信号mF、nFを示し、a、 cはそれぞれ出
力信号mF、nFが逓倍されて生じた信号mpF、nq
Fを示している。In the same figure, d is the voltage controlled oscillator 14.1.
5, and a and c are the signals mpF and nq generated by multiplying the output signals mF and nF, respectively.
It shows F.
第3図に唱いて、信号mpFとrrLF、および信号n
qFとnF の周波数と位相関係は逓倍回路によって定
1す、逓倍回路のフィルタが変動しなければ不変である
。As shown in FIG. 3, the signals mpF and rrLF, and the signal n
The frequency and phase relationship between qF and nF is fixed by the multiplier circuit and remains unchanged unless the filter of the multiplier circuit changes.
このように従来方式にむける位相比較方法は最小公倍数
の周波数1″c逓倍してから位相比較を行なう方法であ
る。As described above, the conventional phase comparison method is a method in which the least common multiple frequency is multiplied by 1''c and then phase comparison is performed.
このような方法は次のような欠点を有するものである。Such a method has the following drawbacks.
(1)温度変化および経年変化に伴なう位相ドリフトを
生じやすい。(1) Phase drift is likely to occur due to temperature changes and aging.
すなわち周波数逓倍を行なう場合は、通常、基本波をパ
ルス波形に変換したのちその高調波成分中から所望の高
調波に同調したフィルタを経て所要の信号を取出す。That is, when frequency multiplication is performed, a fundamental wave is usually converted into a pulse waveform, and then a desired signal is extracted from its harmonic components through a filter tuned to a desired harmonic.
従ってフィルタ(通常はLCフィルタである)の温度変
化および経年変化に基づく同調周波数の変化に伴って、
位相ドリフトを生じることが避けがたい。Therefore, as the tuning frequency of the filter (usually an LC filter) changes due to temperature changes and aging,
It is inevitable that phase drift will occur.
(2)高価でありかつ小形化が困難である。(2) It is expensive and difficult to downsize.
上述の高調波信号抽出用のフィルタは、正確な位相調整
を必要とするため、通常、可変同調形フィルタを使用し
て、出力の振幅と位相を調整して所望の特性を得ている
。Since the above-described filter for extracting harmonic signals requires accurate phase adjustment, a variable tuning filter is usually used to adjust the amplitude and phase of the output to obtain desired characteristics.
従って無調整化は至難であり、かつ高価なものになる。Therefore, it is extremely difficult and expensive to make no adjustments.
またフィルタの寸法は使用周波数によって異なるが、本
方式では長波帯の周波数を使用するため、小形化するこ
とが困難である。Although the dimensions of the filter vary depending on the frequency used, this method uses a long wave band frequency, so it is difficult to miniaturize the filter.
本発明はこのような従来技術の欠点を除去しようとする
ものであって、その目的は電圧制御発振器または電圧制
御移相器を含む可変周波数能動フィルタと分周回路とを
組合せて用いることによ妙、周波数逓倍を行なうことな
く位相比較を行なうことができる方式を提供することに
ある。The present invention attempts to eliminate such drawbacks of the prior art by using a variable frequency active filter including a voltage controlled oscillator or a voltage controlled phase shifter in combination with a frequency dividing circuit. The purpose of this invention is to provide a method that can perform phase comparison without frequency multiplication.
この目的を達成するため本発明のデツカ受信装置の位相
比較方式に釦いては、電圧制御発振器、または電圧制御
発振器の信号を移相する電圧制御移相器と該電圧制御発
振器または電圧制御移相器の出力信号を分周する分周器
とを含み、該分周器の出力信号と受信信号とを位相比較
してその位相差出力により前記電圧制御発振器または電
圧制御移相器を制御して受信信号と一定の位相関係にあ
る逓倍波を発生する能動フィルタを主局用あ・よび従局
用として具え、該主局用釦よび従局用能動フィルタにむ
ける電圧制御発振器または電圧制御移相器の出力信号を
そのtitたは前記能動フィルタのループ内に含まれる
分周器を経て取り出して位相を比較して主局信号と従局
信号の間の位相差を検出することを特徴としている。To achieve this purpose, the phase comparison method of the digital receiver of the present invention includes a voltage controlled oscillator or a voltage controlled phase shifter that shifts the phase of the signal of the voltage controlled oscillator, and a voltage controlled oscillator or voltage controlled phase shifter that shifts the phase of the signal of the voltage controlled oscillator. a frequency divider that divides the frequency of the output signal of the frequency divider, the output signal of the frequency divider and the received signal are compared in phase, and the voltage controlled oscillator or the voltage controlled phase shifter is controlled by the phase difference output. Active filters that generate multiplied waves having a constant phase relationship with the received signal are provided for the main station and the slave station, and a voltage controlled oscillator or voltage controlled phase shifter for the main station button and the slave station active filter is provided. It is characterized in that the output signal is taken out through a frequency divider included in the tit or the loop of the active filter and the phases are compared to detect the phase difference between the main station signal and the slave station signal.
以下実施例について説明する。Examples will be described below.
第3図は本発明のデツカ受信装置の位相比較方式の一実
施例の構成を示すブロック図である。FIG. 3 is a block diagram showing the configuration of an embodiment of the phase comparison method of the digital receiver of the present invention.
同図にむいて第1図の場合と同じ構成部分は同じ符号で
示されている。Components in this figure that are the same as those in FIG. 1 are designated by the same reference numerals.
22.23は電圧制御発振器、24.25は分周回路で
ある。22.23 is a voltage controlled oscillator, and 24.25 is a frequency dividing circuit.
第3図に釦いて受信入力から中間周波増幅器10.11
の出力1での構成釦よび動作は、第1図の場合と同様で
ある。Click the button in Figure 3 to connect the receiving input to the intermediate frequency amplifier 10.11.
The configuration buttons and operations at output 1 are the same as in FIG.
電圧制御発振器22.23はそれぞれmpF、nqFの
周波数の信号を発生し、これらの信号はそれぞれ分周回
路24.25に加えられて、それぞれp分周、q分周さ
れて、それぞれ出力mF、nFを生じる。Voltage controlled oscillators 22 and 23 generate signals with frequencies of mpF and nqF, respectively, and these signals are applied to frequency divider circuits 24 and 25, where they are divided by p and q, respectively, to output mF and nqF, respectively. yields nF.
位相差検出回路12は分周器24の出力と中間周波増幅
器10の出力mFとを比較して位相差に応じた出力を生
じる。The phase difference detection circuit 12 compares the output of the frequency divider 24 and the output mF of the intermediate frequency amplifier 10, and generates an output according to the phase difference.
この出力は低域フィルタ16を経て平滑化されて電圧制
御発振器22に帰還されて位相差出力が零に近づくよう
に発振周波数の制御が行なわれて、電圧制御発振器22
の出力mpFは中間周波信号mFと位相同期される。This output is smoothed through a low-pass filter 16 and fed back to the voltage controlled oscillator 22, where the oscillation frequency is controlled so that the phase difference output approaches zero, and the voltage controlled oscillator 22
The output mpF of is phase-locked with the intermediate frequency signal mF.
電圧制御発振器22、分周回路24、位相差検出回路1
2、低域フィルタ16は第1図の場合と同様に狭帯域の
可変周波数能動フィルタとして動作する。Voltage controlled oscillator 22, frequency dividing circuit 24, phase difference detection circuit 1
2. The low pass filter 16 operates as a narrow band variable frequency active filter as in FIG.
同様にして電圧制御発振器23、分周回路25、位相差
検出回路13、低域フィルタ17は狭帯域の可変周波数
能動フィルタを形成し、電圧制御発振器23は中間周波
増幅器11の出力nFと位相同期した周波数nqFの出
力を生じる。Similarly, the voltage controlled oscillator 23, the frequency dividing circuit 25, the phase difference detection circuit 13, and the low-pass filter 17 form a narrow band variable frequency active filter, and the voltage controlled oscillator 23 is phase synchronized with the output nF of the intermediate frequency amplifier 11. produces an output with a frequency nqF.
ここで信号mpFと信号nqFとの間で基本周波数Fに
対する倍率mp=nqとなるように選ばれている。Here, the signal mpF and the signal nqF are selected so that the magnification mp=nq for the fundamental frequency F is satisfied.
位相差検出回路20は電圧制御発振器22の出力mpF
と、電圧制御発振器23の出力nqF とを位相比較し
て位相差に応じた出力を発生し、位相差指示器21はこ
れを指示する。The phase difference detection circuit 20 uses the output mpF of the voltage controlled oscillator 22.
and the output nqF of the voltage controlled oscillator 23 to generate an output according to the phase difference, and the phase difference indicator 21 indicates this.
第4図は第3図に示された本発明の方式にち・ける各部
信号の周波数と位相関係を示す波形図である。FIG. 4 is a waveform diagram showing the frequency and phase relationships of various signals in the system of the present invention shown in FIG.
同図にち−いてaは電圧制御発振器22または23の出
力信号波形、bは電圧制御発振器出力信号を方形波に変
換した信号波形、Cは分周器24捷たは25の出力信号
波形、dは分周器出力信号波形の正弦波成分を示してい
る。In the figure, a is the output signal waveform of the voltage controlled oscillator 22 or 23, b is the signal waveform obtained by converting the voltage controlled oscillator output signal into a square wave, C is the output signal waveform of the frequency divider 24 or 25, d indicates a sine wave component of the frequency divider output signal waveform.
位相差検出回路12寸たは13に耘ける位相比較は、第
4図Cに示された分周器出力信号または同図dに示され
たその正弦波成分と中間周波出力信号との間で行なわれ
、その結果によって電圧制御発振器を制御して第4図a
に示された出力信号の周波数を変化させて、分周器出力
信号またはその正弦波成分を中間周波信号に位相同期さ
せる。Phase comparison using the phase difference detection circuit 12 or 13 is performed between the frequency divider output signal shown in FIG. 4C or its sine wave component shown in FIG. 4D and the intermediate frequency output signal. The voltage controlled oscillator is controlled according to the result and the voltage controlled oscillator is controlled as shown in FIG.
The frequency of the output signal shown in is varied to phase-lock the frequency divider output signal or its sinusoidal component to the intermediate frequency signal.
ここで第4図すに示された分周前の信号と同図Cに示さ
れた分周後の信号との位相関係は、分周器の動作開始時
の状態によって定1す、動作途中で変ることはない。Here, the phase relationship between the pre-frequency-divided signal shown in Figure 4 and the frequency-divided signal shown in Figure 4C is determined by the state of the frequency divider at the start of operation. It won't change.
このため電源投入ごとに分周前の信号と分周後の信号と
の位相関係は変化することが考えられるが、その変化の
度合いは、分周前信号の位相で2π(rad)tたは】
サイクルの整数倍で変化する。Therefore, the phase relationship between the pre-divided signal and the divided signal may change each time the power is turned on, but the degree of this change is 2π (rad)t or ]
Changes in integer multiples of cycles.
しかしながら主局と従局間の受信信号の位相差は、第4
図aに示された電圧制御発振器出力信号または同図すに
示された方形波信号に相当する信号の間の1サイクルの
範囲内で測定されるため、これらの信号が1サイクルの
整数倍でその位相が変化しても測定には何ら支障なく、
また測定誤差を生じることもない。However, the phase difference of the received signal between the master station and the slave station is
Since these signals are measured within one cycle between the voltage-controlled oscillator output signal shown in Figure a or the signal corresponding to the square wave signal shown in Figure a, it is assumed that these signals are integer multiples of one cycle. Even if the phase changes, there is no problem in measurement.
Moreover, no measurement error occurs.
このように能動フィルタを構成する電圧制御発振器の発
振周波数を中間周波数の整数倍の比較周波数(mpFt
たはnqF)としたことによって逓倍器を使用すること
なく、主従両局の信号の位相比較を行なうことができる
。In this way, the oscillation frequency of the voltage controlled oscillator constituting the active filter is set to a comparison frequency (mpFt
or nqF), it is possible to compare the phases of the signals of both the master and slave stations without using a multiplier.
第5図は本発明のデツカ受信装置の位相比較方式の他の
実施例の構成を示すブロック図である。FIG. 5 is a block diagram showing the configuration of another embodiment of the phase comparison method of the digital receiver according to the present invention.
同図において31は受信空中線、32.33は高周波増
幅器、34.35は混合回路、36.3Tは分周回路、
38.39は中間周波増幅器、40.41は位相差検出
回路、42は混合回路、43は電圧制御発振器、44は
基準発振器、45は分周回路、46は低域フィルタ、4
7は逓倍器、48は電圧制御移相器、49は分周回路、
50は低域フィルタ、51は位相差検出回路、52は位
相差指示器、53は可変周波数発振器、54は混合回路
、55は帯域フィルタ、56は可変分周回路、57は受
信チェーン設定器、58は固定分周回路、59は位相差
検出回路、60は低域フィルタである。In the figure, 31 is a receiving antenna, 32.33 is a high frequency amplifier, 34.35 is a mixing circuit, 36.3T is a frequency dividing circuit,
38.39 is an intermediate frequency amplifier, 40.41 is a phase difference detection circuit, 42 is a mixing circuit, 43 is a voltage controlled oscillator, 44 is a reference oscillator, 45 is a frequency dividing circuit, 46 is a low-pass filter, 4
7 is a multiplier, 48 is a voltage controlled phase shifter, 49 is a frequency dividing circuit,
50 is a low-pass filter, 51 is a phase difference detection circuit, 52 is a phase difference indicator, 53 is a variable frequency oscillator, 54 is a mixing circuit, 55 is a band filter, 56 is a variable frequency dividing circuit, 57 is a reception chain setter, 58 is a fixed frequency dividing circuit, 59 is a phase difference detection circuit, and 60 is a low-pass filter.
第5図にち−いて空中線31の受信入力(主局6f、従
局5f)は、それぞれ高周波増幅器32.33で増幅さ
れ、それぞれ混合回路34.35に勢いてそれぞれ分周
器36.37で発生した局発信号6A、5Aと混合され
て、中間周波数信号としてそれぞれ6F、5Fを生じる
。In FIG. 5, the receiving inputs of the antenna 31 (main station 6f, slave station 5f) are amplified by high-frequency amplifiers 32, 33, respectively, and sent to mixing circuits 34, 35, respectively, and generated by frequency dividers 36, 37. The received local oscillator signals 6A and 5A are mixed to produce intermediate frequency signals 6F and 5F, respectively.
これらの中間周波数信号はそれぞれ中間周波増幅器38
.39で増幅されたのちそれぞれ位相差検出回路40.
41へ加えられる。Each of these intermediate frequency signals is sent to an intermediate frequency amplifier 38.
.. After being amplified by phase difference detection circuit 40.
Added to 41.
一方、混合回路42は電圧制御発振器43の信号f と
基準発振器44の信号fRとを混合して差周波数の信号
1080Fを発生する。On the other hand, the mixing circuit 42 mixes the signal f 1 from the voltage controlled oscillator 43 and the signal fR from the reference oscillator 44 to generate a signal 1080F of the difference frequency.
信号1080Fは分周回路45で180分周されて信号
6Fを生じ位相差検出回路40へ加えられる。The signal 1080F is frequency-divided by 180 by the frequency dividing circuit 45 to generate a signal 6F, which is applied to the phase difference detection circuit 40.
位相差検出回路40は両信号を比較して位相差に応じた
出力を発生し、この出力は低域フィルタ46を経て電圧
制御発振器43に帰還されてその発振周波数を制御する
。The phase difference detection circuit 40 compares both signals and generates an output according to the phase difference, and this output is fed back to the voltage controlled oscillator 43 via a low-pass filter 46 to control its oscillation frequency.
電圧制御発振器43、混合回路42、分周器45、位相
差検出回路40、低域フィルタ46は第3図の場合と同
様な狭帯域の可変周波数能動フィルタを構成している。The voltage controlled oscillator 43, mixing circuit 42, frequency divider 45, phase difference detection circuit 40, and low pass filter 46 constitute a narrow band variable frequency active filter similar to that shown in FIG.
また混合回路42の出力信号1080Fは逓倍器47に
むいて4逓倍されて信号4320Fを生じる。Further, the output signal 1080F of the mixing circuit 42 is sent to a multiplier 47 and multiplied by 4 to produce a signal 4320F.
信号4320Fは電圧制御移相器48に加えられて(1
44±1)分周されて出力信号30Fを生じる。Signal 4320F is applied to voltage controlled phase shifter 48 (1
44±1) to produce output signal 30F.
出力信号30Fは分周回路49において6分周されて出
力信号5Fを生じ、位相差検出回路41に加えられる。The output signal 30F is frequency-divided by 6 in the frequency divider circuit 49 to generate an output signal 5F, which is applied to the phase difference detection circuit 41.
位相差検出回路41は両信号を比較して位相差に応じた
出力を発生し、この出力は低域フィルタ50を経て電圧
制御移相器48に帰還されてその分周比を制御し、結果
的に出力周波数を制御する。The phase difference detection circuit 41 compares both signals and generates an output according to the phase difference, and this output is fed back to the voltage-controlled phase shifter 48 through a low-pass filter 50 to control its frequency division ratio. control the output frequency.
電圧制御移相器48、分周回路49、位相差検出回路4
L低域フイルタ50は同様に狭帯域の可変周波数能動フ
ィルタを構成している。Voltage control phase shifter 48, frequency divider circuit 49, phase difference detection circuit 4
The L low-pass filter 50 similarly constitutes a narrow band variable frequency active filter.
分周回路45にトける36分周出力30Fと電圧制御移
相器48の出力信号30Fとは位相差検出回路51にむ
いて位相比較されて位相差に応じた出力を生じ、位相差
指示器52はこれを指示する
可変周波数発振器53は局発周波数信号
1080Jを発生する。The 36 frequency divided output 30F to the frequency dividing circuit 45 and the output signal 30F of the voltage controlled phase shifter 48 are phase-compared and sent to a phase difference detection circuit 51 to produce an output according to the phase difference, and a phase difference indicator. A variable frequency oscillator 53, designated by 52, generates a local frequency signal 1080J.
この信号は混合回路54に釦いて基準発振器44の信号
と混合され、帯域フィルタ55で所望の周波数帯を選択
的にとり出したのち可変分周回路56で分周する。This signal is mixed with the signal from the reference oscillator 44 by a mixing circuit 54, selectively extracting a desired frequency band by a bandpass filter 55, and then divided by a variable frequency dividing circuit 56.
1A変分周回路560分周比は受信チェーン設定器57
によって外部的に設定され得る。1A variable frequency divider circuit 560 frequency division ratio is receive chain setter 57
Can be set externally by
一方、固定分周回路58は基準発振器44の出力信号f
Rを固定分周比で分周する。On the other hand, the fixed frequency divider circuit 58 receives the output signal f of the reference oscillator 44.
Divide R using a fixed frequency division ratio.
両分周回路の出力信号は位相差検出回路59で位相比較
されて位相差に応じた出力を生じる。The output signals of both frequency dividing circuits are phase-compared by a phase difference detection circuit 59 to generate an output according to the phase difference.
この出力は低域フィルタ60を経て可変周波数発振器5
3の発振周波数を制御して基準発振器44に位相同期さ
せる。This output is passed through a low-pass filter 60 to a variable frequency oscillator 5.
The oscillation frequency of the reference oscillator 44 is controlled to achieve phase synchronization with the reference oscillator 44.
このように可変周波数発振器53を含むループはシンセ
サイザ回路を構成し受信チェーンに対応して一定周波数
間隔て局発周波数信号を発生する。In this way, the loop including the variable frequency oscillator 53 constitutes a synthesizer circuit, and generates local oscillation frequency signals at constant frequency intervals in correspondence with the receiving chain.
可変周波数発振器53の発生した局発周波数信号] 0
80Jは、分周回路36で180分周され、捷た分周回
路37で216分周されてそれぞれ6A、5Aの信号を
発生し、前述のようにそれぞれ混合回路34.35に加
えられる。Local oscillator frequency signal generated by variable frequency oscillator 53] 0
80J is frequency-divided by 180 in the frequency divider circuit 36, and frequency-divided by 216 in the divided frequency divider circuit 37 to generate signals of 6A and 5A, respectively, which are respectively applied to the mixing circuits 34 and 35 as described above.
第5図に示された実施例にむいて、信号fvは第3図の
実施例における信号mpFに相当している。For the embodiment shown in FIG. 5, signal fv corresponds to signal mpF in the embodiment of FIG.
しかしながら本実施例の方式にむいては、選択度向上の
目的から中間周波数を著しく低く選定しているので、局
発基準信号fRの周波数ドリフトが問題になるため、信
号fRとfvのビート差から信号mF(6F)、mpF
(30F)を得るように構成することによってこれを解
決している。However, in the method of this embodiment, the intermediate frequency is selected to be extremely low for the purpose of improving selectivity, so the frequency drift of the local reference signal fR becomes a problem. Signal mF (6F), mpF
This is solved by configuring to obtain (30F).
以上説明したように本発明のデツカ受信装置の位相比較
方式によれば、逓倍回路を使用しないことによって回路
を無調整化できるとともに、分周に伴なう位相変化が極
めて小さい(通常ディジタルICの温度変化による立下
り、立下り遅延時間変化は非常に小さい)ので、安定度
の極めて高い位相比較方式が実現でき、しかも安価であ
り、優れた効果が得られる。As explained above, according to the phase comparison method of the digital receiver of the present invention, the circuit can be made without adjustment by not using a multiplier circuit, and the phase change due to frequency division is extremely small (usually compared to digital ICs). (The fall and fall delay time changes due to temperature changes are very small.) Therefore, a phase comparison method with extremely high stability can be realized, and it is inexpensive and provides excellent effects.
第1図は従来のデツカ受信装置にむける位相比較方式の
構成を示すブロック図、第2図は第1図の方式にむける
各部信号の周波数と位相関係を示す波形図、第3図は本
発明のデツカ受信装置の位相比較方式の一実施例の構成
を示すブロック図、第4図は第3図の方式における各部
信号の周波数と位相関係を示す波形図、第5図は本発明
のデツカ受信装置の位相比較方式の他の実施例の構成を
示すブロック図である。
1・・・受信空中線、2.3・・・高周波増幅器、4.
5・・・混合回路、6・・・局発原振回路、7・・・M
分周およびパルス整形回路、8.9・・・逓倍器、10
.11・・・中間周波増幅器、12.13・・・位相差
検出回路、14.15・・・電圧制御発振器、16.1
7・・・低域フィルタ、18.19・・・逓倍器、20
・・・位相差検出回路、21・・・位相差指示器、22
.23・・・電圧制御発振器、24.25・・・分周回
路、31・・・受信空中線、32.33・・・高周波増
幅器、34.35・・・混合回路、36.37・・・分
周回路、38.39・・・中間周波増幅器、40.41
・・・位相差検出回路、42・・・混合回路、43・・
・電圧制御発振器、44・・・基準発振器、45・・・
分周回路、46・・・低域フィルタ、47・・・逓倍器
、48・・・電圧制御移相器、49・・・分周回路、5
0・・・低域フィルタ、51・・・位相差検出回路、5
2・・・位相差指示器、53・・・可変周波発振器、5
4・・・混合回路、55・・・帯域フィルタ、56・・
・可変分周回路、57・・・受信チェーン設定器、58
・・・固定分周回路、59・・・位相差検出回路、60
・・・低域フィルタ。Fig. 1 is a block diagram showing the configuration of a phase comparison method for a conventional digital receiver, Fig. 2 is a waveform diagram showing the frequency and phase relationship of each part signal for the method shown in Fig. 1, and Fig. 3 is a diagram of the present invention. FIG. 4 is a waveform diagram showing the frequency and phase relationship of each part of the signal in the method of FIG. 3, and FIG. FIG. 3 is a block diagram showing the configuration of another embodiment of the phase comparison method of the device. 1... Receiving antenna, 2.3... High frequency amplifier, 4.
5...Mixing circuit, 6...Local oscillator circuit, 7...M
Frequency division and pulse shaping circuit, 8.9...multiplier, 10
.. 11... Intermediate frequency amplifier, 12.13... Phase difference detection circuit, 14.15... Voltage controlled oscillator, 16.1
7...Low pass filter, 18.19...Multiplier, 20
... Phase difference detection circuit, 21 ... Phase difference indicator, 22
.. 23... Voltage controlled oscillator, 24.25... Frequency dividing circuit, 31... Receiving antenna, 32.33... High frequency amplifier, 34.35... Mixing circuit, 36.37... Min. Frequency circuit, 38.39...Intermediate frequency amplifier, 40.41
...Phase difference detection circuit, 42...Mixing circuit, 43...
・Voltage controlled oscillator, 44... Reference oscillator, 45...
Frequency divider circuit, 46...Low pass filter, 47...Multiplier, 48...Voltage control phase shifter, 49...Frequency divider circuit, 5
0...Low pass filter, 51...Phase difference detection circuit, 5
2... Phase difference indicator, 53... Variable frequency oscillator, 5
4...Mixing circuit, 55...Band filter, 56...
・Variable frequency divider circuit, 57... Receive chain setting device, 58
. . . Fixed frequency dividing circuit, 59 . . . Phase difference detection circuit, 60
...Low pass filter.
Claims (1)
相する電圧制御移相器と該電圧制御発振器または電圧制
御移相器の出力信号を分周する分周器とを含み、該分周
器の出力信号と受信信号とを位相比較してその位相差出
力により前記電圧制御発振器または電圧制御移相器を制
御して受信信号と一定の位相関係にある逓倍波を発生す
る能動フィルタを主局用督よび従局用として具え、該主
局用も−よび従局用能動フィルタに釦ける電圧制御発振
器または電圧制御移相器の出力信号をその11捷たは前
記能動フィルタのループ内に含1れる分周器を経て取り
出して位相を比較して主局信号と従局信号の間の位相差
を検出することを特徴とするデツカ受信装置の位相比較
方式。1 includes a voltage controlled oscillator or a voltage controlled phase shifter that shifts the phase of the signal of the voltage controlled oscillator, and a frequency divider that divides the output signal of the voltage controlled oscillator or the voltage controlled phase shifter, An active filter for the main station that compares the phases of the output signal and the received signal and controls the voltage controlled oscillator or voltage controlled phase shifter using the phase difference output to generate a multiplied wave having a constant phase relationship with the received signal. The output signal of a voltage controlled oscillator or a voltage controlled phase shifter provided for the master station and the slave station, and which is switched to the active filter for the master station and the slave station, is divided into 11 or 1 part included in the loop of the active filter. A phase comparison method for a DETSUKA receiving device characterized by detecting a phase difference between a main station signal and a slave signal by extracting the signal through a frequency converter and comparing the phases.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15122979A JPS5853870B2 (en) | 1979-11-21 | 1979-11-21 | Decca receiver phase comparison method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15122979A JPS5853870B2 (en) | 1979-11-21 | 1979-11-21 | Decca receiver phase comparison method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5673369A JPS5673369A (en) | 1981-06-18 |
| JPS5853870B2 true JPS5853870B2 (en) | 1983-12-01 |
Family
ID=15514060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15122979A Expired JPS5853870B2 (en) | 1979-11-21 | 1979-11-21 | Decca receiver phase comparison method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5853870B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60252173A (en) * | 1984-05-29 | 1985-12-12 | Furukawa Mining Co Ltd | Piston pump |
| JPS6170585U (en) * | 1984-10-15 | 1986-05-14 |
-
1979
- 1979-11-21 JP JP15122979A patent/JPS5853870B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60252173A (en) * | 1984-05-29 | 1985-12-12 | Furukawa Mining Co Ltd | Piston pump |
| JPS6170585U (en) * | 1984-10-15 | 1986-05-14 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5673369A (en) | 1981-06-18 |
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