JPS5854548B2 - Jiyouhouno Jitsutayokusei Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention also relates to a jitter suppression circuit that compensates for zero jitter (time axis fluctuation) in reproduced video information reproduced from a VTR (video tape recorder), video disc player, or the like.

Generally, when transmitting information, a phase shift may occur.

It is well known that the image displayed on a monitor TV by a reproduced video signal containing a phase shift, that is, a jitter component (a time axis fluctuation component), has a horizontal shaking phenomenon, and that it is difficult to see the screen V. In order to eliminate this problem, efforts have been made in various fields.

In broadcast VTRs, there is a jitter component suppression circuit generally called a color tick.

In other words, Kome Colortic uses a variable delay line and a fixed delay line to delay the signal component in advance in order to suppress the jitter component, and both of these delay lines handle the Φ jitter component in the wideband video signal of 4 MHz. It requires a large number of capacitors and coils for suppression, and its inductance and capacitance are strictly regulated, so it is technically difficult to manufacture, expensive, and requires a large amount of space. It is said that

This paperIt is almost impossible to apply this technology as is to simple VTRs for home use, so in simple VTRs the jitter component is suppressed by servo-related control, but the suppression effect is very low. is not the ratio of broadcast VTR.

By the way, there are variable delay lines as shown in FIG.

That is, this variable delay line includes capacitors C1 to Cn. C1'
~Cn' and MO connected correspondingly to this capacitor
It is composed of 8-type transistors T1 to Tn and T1' to Tn', and its operation will be explained as follows.
A video signal is introduced into the input terminal IN, and a sampling clock signal φ1. φ2 is each clock signal input terminal G
1. Introduced in G2.

This clock signal φ1. φ2 are pulses of different polarity with the same frequency, and when the clock signal φ1 is introduced into one input terminal G1, the MO8 type transistor and transistor T1
In the charge/discharge circuit 1 consisting of a capacitor C1 and a transistor T1, the transistor T1 is turned on, and the video signal is charged to the capacitor C1 through the source and drain of the transistor T1. . . . are transistors T3, . T5...
Capacitors C3 and C5 through the source and drain of
Charge it to...

Therefore, the video signal is charged to the capacitor with an amount of charge corresponding to the signal content, and each time a clock signal is introduced, the signal content is transmitted to the next stage charging/discharging circuit. Signal φ1. By controlling the frequency of φ2, it is possible to determine how much the transmission phase of the video signal is delayed.

The present invention provides a jitter suppression circuit including such a delay line KT, and is intended to eliminate the above-mentioned problems by devising a circuit for employing this delay line.

That is, in general, when suppressing jitter components using a delay line, in order to perform the jitter suppression operation as faithfully as possible, it is desirable to match the delay time due to the delay line with the delay time in the jitter distribution detection control loop.

Furthermore, especially when suppressing jitter in a reproduced video signal,
Since the jitter component is usually detected based on the horizontal synchronization signal, more faithful jitter suppression operation can be performed by increasing the delay time of the delay line to IH (here, H is horizontal period open) or an integer multiple thereof. obtain.

However, in order to delay a video signal by more than IH (here, H is the period of the horizontal synchronization signal) using a variable delay line as described above, a very large number of delay line components are required and the cost is high. In the present invention, an inexpensive variable delay line with a relatively small amount of delay is used, and by combining this with an ordinary fixed delay line, the video signal is delayed by IH (nH if necessary), thereby eliminating the jitter component in the video signal. The present invention provides a jitter suppression circuit that can eliminate jitter.

FIG. 2 is a diagram illustrating a circuit 0) 1 according to the present invention,
To explain based on the figure, a video signal containing a jitter component is introduced to the terminal (1).

In the case of a television signal, this video signal includes a synchronization signal, but only the horizontal synchronization signal in this synchronization signal is separated from other video signal components in a synchronization separation circuit DB, and the horizontal synchronization signal is transferred to a phase comparison circuit described later. Introduce it to IH.

Note that this horizontal synchronization signal is 15.734 KHz in the case of color television signals.

In the case of black and white television signals, the frequency is 15.75 KHz.

KS is a reference signal generation circuit using a crystal, and if it is related to the former color television signal, it is 15.734 KH.
z1 If the latter is related to black and white television signals, 1
Accurately outputs a 5.75 KHz signal.

Further, this circuit KS may output the average value of the horizontal synchronization signal of the video signal including jitter.

Then, based on the reference signal from the reference signal generation circuit KS, the sawtooth wave generation circuit NH is driven to output a sawtooth wave.

This sawtooth wave is then introduced into the phase comparator circuit IH.

This circuit IH is used as an input to compare the phase of the horizontal synchronization signal, which is synchronously separated by the synchronous separation circuit DB and is out of phase if a jitter component is included, and the sawtooth wave, which is not out of phase, from the sawtooth wave generation circuit NH. a.

The output is shown in the same figure.

That is, when the video signal does not contain a jitter component, no phase shift occurs in the video signal, and the synchronization signal is located at the center of the slope of the sawtooth wave, that is, at the time t1 in FIG. Comparison circuit IH has level A according to its position.
Derive the output of .

Next, the video signal contains jitter components, so
When the horizontal synchronization signal is delayed in phase, that is, when the time t2 coincides with the point after the center of the slope of the sawtooth wave (so-called delay jitter), the phase comparator circuit IH derives an output of level B. .

Conversely, in the case of progressive jitter, the circuit IH derives an output of level C.

A specific example of this phase comparison circuit IH is shown in FIG.

A horizontal synchronizing signal is applied to the base of this transistor T, a sawtooth wave pulse is applied to the collector, and their gate output charges a capacitor between the emitter of the transistor and ground, and the amount of this charge is shown in Figure 3. It is shown.

Further, GZ is an output amplification circuit of the phase comparator circuit JH,
■CO is an oscillator (using a varicap, for example) that changes its own oscillation frequency based on the input voltage level, and the phase comparator circuit IH uses an introductory mole level, which is information 0 phase information due to jitter components included in the video signal. This is a problem in which the oscillation frequency can be changed depending on the degree of advance or lag.

Furthermore, in the case of leading jitter, the oscillation frequency of the oscillator 2CO becomes low, and conversely, in the case of lagging jitter, the oscillation frequency becomes high.

Therefore, when there is no jitter component in the video signal, the output voltage of the phase comparator (HO) is at A level, and at this time the fundamental oscillation frequency of the oscillator (CO) is f.

shall be.

This oscillation frequency f. A sampling pulse corresponding to the output voltage is derived from the next-stage drive circuit SD and introduced into the input terminals Gl and G2 (FIG. 1) of the variable delay line KT.

This sampling pulse becomes the aforementioned clock signal, and this signal causes the video signal on the input side of the variable delay line KT to pass through the variable delay line KT for a time t.

The phase of minutes is delayed.

When a jitter component is included in a video signal, the phase of the video signal is delayed depending on the content of the jitter component.

Next, the most characteristic part of the present invention will be mentioned.

That is, it is the modulation circuit HK and fixed delay line K in FIG.
It is OT.

Generally, an ultrasonic delay line has a bandwidth of only about 60% of its center frequency, so when handling a video signal with a bandwidth of 4 MHz, the bandwidth of the video signal is 1.4 MHz or lower and 2.6 MHz or higher. Parts will be cut.

To solve this problem, the video signal is transferred to carrier 9MH.
z SBM modulation is performed to set the center frequency to 7 MHz.

(FIG. 6A→B) Here, this video signal includes a chromaticity signal.

Since the center frequency is 7 MHz, a bandwidth of 60% can sufficiently cover the video signal band.

This modulation circuit HK is not used in broadcast VTRs because the expensive and large ultrasonic fixed delay line has a sufficiently large bandwidth to cover the video signal band.
In an embodiment of the present invention, a small and low-cost ultrasonic fixed delay line K
In order to use OT, a modulation circuit HK is provided.

Next, the fixed delay line KOT changes the phase of the video signal to IH (63
, 5μs) is several μs shorter than (63,5μs).

).On the other hand, the variable delay line KT has the function of delaying the video signal by the delay time of KS.On the other hand, when the video signal does not contain any jitter components, the variable delay line KT delays the phase of the video signal by τ.

The signal controlled by the clock signal to be delayed by the delay time of KS is 0.

Note that MOD is a demodulation circuit that demodulates the SBM-modulated video signal in the modulation circuit HK, but this demodulates no jitter component.

According to the circuit shown in FIG. 2, when it is assumed that the video signal introduced to the input terminal 1 does not contain a jitter component, the delay time of the fixed delay line KOT is (63,5-τ).

) KS and the delay time T of the variable delay line KT.

The total of KS corresponds to 63.5 μs, that is, IH (horizontal synchronizing signal Φ period), and the demodulator MOD has an input terminal V1.
A signal that is delayed by exactly IH with respect to the phase of the signal 0) introduced into is derived.

When the video signal contains a jitter component (lead jitter and zero phase delay amount converted into delay time δμs), the delay time of variable delay line KT is (τ0 + δ).
μs1 On the other hand, the delay time of the fixed delay line KOT is (63, 5
-τ0 )KS, so the total is (63,5+δ
) KS, and even if the video signal includes jitter δ, the total delay time is (63,5+δ)KS, resulting in a delay of 63.5 μs, that is, IH.

Also, in the case of reverse delay jitter, there will be a delay by IH.

As described above, according to the jitter suppression circuit of the present invention, even when an inexpensive variable delay line with a relatively small amount of delay is used, in combination with a fixed delay line, the phase of information is always IH (if necessary, nH). ) minutes.

As a result, the delay time due to the delay line and the delay time in the jitter component detection control loop can be made to substantially match, and as a result, the jitter component in the video signal can be faithfully removed without any time delay.

Therefore, if the reproduced video signal obtained through the jitter suppression circuit of the present invention is supplied to a monitor television, the time axes of each scanning line will be aligned, and no image lateral movement will occur.

In the above embodiment, the phase comparator circuit IH performs the phase comparison using H pulses, but it may also use a burst signal of a color television signal.

However, in this case, a burst signal extraction circuit BK (FIG. 5) is required in place of the synchronous separation circuit DB.

That is, the stiffness circuit BK connects the input terminal V1 and the phase comparator circuit I.
A gate circuit GK is inserted between H pulses, and a series circuit of an H pulse separation circuit HB and a burst flag circuit BK is inserted in parallel with this circuit GK.

In this case, the reference signal of the reference signal generation circuit KS is 35.8
MHz O) subcarrier (Konaru).

[Brief explanation of the drawing]

FIG. 1 is a variable delay diagram according to the present invention, FIG. 2 is a diagram illustrating one embodiment of a jitter suppression circuit block according to the present invention, FIG. 3 is an input/output relationship diagram of the phase comparator circuit, and FIG. 4 is a diagram of the phase comparator circuit. FIG. 5 is a diagram showing another embodiment of the present invention, and FIG. 6 is a frequency characteristic diagram for explaining the operation of the present invention. KT2 variable delay line, SD: sampling drive circuit,
VCO: Voltage variable oscillator, KS: Reference signal generator, NH
: Sawtooth wave generation circuit, ■H: Phase comparator circuit, DB two-sync separation circuit, KOT: Fixed delay line.

Claims (1)

[Scope of Claims] 1. A variable delay unit having a function of delaying the phase of information according to the content of a clock signal, which determines the amount of delay of the information phase by the variable delay unit when the information does not include a jitter component. A fixed delay unit that increases the total information phase delay amount by nH (n is a natural number) when added to the information phase delay amount, a jitter component detection circuit that detects the jitter component based on the horizontal periodic signal in the above information, and this circuit. An information jitter suppression circuit comprising: a derivation circuit for deriving the clock signal having content corresponding to the detected content; and means for introducing the clock signal output from the derivation circuit into the variable delay section.