JPS585528B2 - Parallel connection circuit of transistors - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor circuit including a plurality of transistors connected in parallel to each other.

When using transistors as individual conversion valves in static power conversion devices such as choppers and inverters, it is possible to increase the current capacity of the device by configuring each conversion valve with multiple transistors connected in parallel with each other. can.

In this case, in order to maximize the overall current capacity with the same number of parallel transistors, the transistors must share the current equally.

Regarding current sharing when all transistors are in a completely saturated state, if the transistors are of the same standard, even if there are some variations in characteristics, an imbalance in current sharing that would become a problem generally does not occur.

Also, when the transistor turns on, the overall current cannot rise rapidly to a large value due to the circuit inductance, so it is only necessary to shorten the on time by over-controlling the transistor for a short time. , excessive current will not be concentrated in a particular transistor.

However, when a transistor is turned off while a large load current is flowing, this large load current does not suddenly decrease due to circuit inductance, so the current concentrates on the transistor that has a long off time.

In general, even transistors of the same standard have considerable variation in off-time characteristics, and for this reason, conventional methods have been unable to fully utilize the capabilities of individual transistors, and the aim was to increase the current capacity of the entire device. was not fully accomplished.

An object of the present invention is to compensate for variations in off-time characteristics of individual transistors by simple means to avoid excessive current concentration in a particular transistor.

According to the present invention, a resistor is inserted and connected in series to the emitter side of each of a plurality of transistors connected in parallel, and the bases are connected together, and a capacitor is connected between the base and emitter of each transistor. This is achieved by connecting.

The figure is an electrical circuit diagram showing an embodiment of the present invention.

Resistors R1 to Rn are connected to the emitters of n transistors T1 to Tn, which are connected in parallel to each other,
Further, capacitors C1 to Cn are individually connected between the base and emitter.

One auxiliary transistor TB is connected together in Darlington to drive the transistors T1 to Tn.

Here, to simplify the explanation, two transistors T1
, T2 are connected in parallel.

Now, the auxiliary transistor TB is made conductive by a base drive circuit (not shown), and both transistors T1 and T2 are in a saturated state, so that they share partial currents I1 and 2 of the load current IL, respectively. (■1 IL/2 ■2)

In such a state, if the auxiliary transistor TB is turned off by cutting off the pace current, the current of the transistor with a shorter off time, for example T1, decreases from 1.

On the other hand, the current of the transistor T2, which has a longer off-time, increases from ■2. In other words, the total current ■L does not suddenly decrease, so the current of the transistor T2 increases by the amount that the current of the transistor T1 decreases. To increase.

Since a voltage drop occurs in the resistors R1 and R2 inserted on the emitter side of each transistor T1 and T2 in proportion to their respective currents, a difference occurs in their emitter potentials.

That is, the emitter potential of the transistor T2 becomes higher than the emitter potential of the transistor T1.

This potential difference supplies base current to transistor T1 via capacitor C2 and the common base line.

As a result, the off-time of the transistor T2 is lengthened, and an increase in the current of the transistor T2 is suppressed.

The resistor on the emitter side of each transistor serves to generate a voltage (i.e., the above potential difference) to compensate for variations in off-time, and the capacitor connected between the base and emitter of each transistor is It helps form a circuit to supply base current to the transistor that is turned off.

In this way, according to the present invention, all transistors are turned off while suppressing current imbalance by aligning with the longest off time or longer off time among the off times of individual transistors in a single state. can be done.

For example, when two transistors with a difference in off time of μsec are turned off from a state in which each current is approximately 5 OA, R1=R2=10 mΩ, C1
=C2=0.1μF, the transient current increase of the transistor with longer off time is 1% (i.e. 50A)
×0.01=0.5A) and capacitors C1 and C2
It was experimentally confirmed that this is 1/10 or less compared to the case where .

[Brief explanation of the drawing]

The figure is an electrical circuit diagram showing an embodiment of the present invention in which transistors are connected in parallel. T1-Tn: Transistor, C1-Cn: Capacitor,
R1 to Rn: resistance, TB: auxiliary transistor.

Claims (1)

[Claims] 1. A transistor characterized in that a resistor is connected in series to the emitter side of each of a plurality of transistors connected in parallel, the bases are connected together, and a capacitor is connected between the base and emitter of each transistor. Parallel connection circuit.