JPS5855684B2 - FM signal pulse count demodulator - Google Patents
FM signal pulse count demodulatorInfo
- Publication number
- JPS5855684B2 JPS5855684B2 JP50123534A JP12353475A JPS5855684B2 JP S5855684 B2 JPS5855684 B2 JP S5855684B2 JP 50123534 A JP50123534 A JP 50123534A JP 12353475 A JP12353475 A JP 12353475A JP S5855684 B2 JPS5855684 B2 JP S5855684B2
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- output
- signal
- monostable multi
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Description
【発明の詳細な説明】
本発明はFM信号のパルスカウント方式復調装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse count type demodulation device for FM signals.
従来、FM信号を復調する復調装置0一方式としてパル
スカウント方式復調装置があることが知られている。Conventionally, it is known that there is a pulse count type demodulator as one type of demodulator for demodulating an FM signal.
すなわち、第1図に示すように入力端子1に印加された
FM信号をリミッタ回路2で振幅制限し、パルス変換回
路3で一定幅のパルス信号に変換した後積分回路4を介
して出力端子5にオーディオ信号を得るものである。That is, as shown in FIG. 1, the limiter circuit 2 limits the amplitude of the FM signal applied to the input terminal 1, the pulse conversion circuit 3 converts it into a pulse signal of a constant width, and then the signal is sent to the output terminal 5 via the integration circuit 4. It is used to obtain audio signals.
上記従来例ではパルス変換回路3として例えば第2図に
その一回路側を示すような1個の単安定マルチバイブレ
ークが用いられていた。In the conventional example described above, a single monostable multi-vibration circuit such as one of which is shown in FIG. 2, for example, is used as the pulse conversion circuit 3.
ところが、第2図において出力パルス幅は、コンデンサ
C1と、抵抗R1によって決まる時定数の微分パルスと
、回路のスレンユホルドレベルにより決定されるが、コ
ンデンサC1と抵抗R1の接続点には出力パルスの後縁
時に前記前縁時の微分パルスとは逆の極性の微分パルス
を生じるために、FM信号の周波数変化によって出力パ
ルスの各前縁時における上記接続点の電圧は一定になら
ず、その結果出力パルス幅が一定にならなくなって復調
歪を発生する。However, in Fig. 2, the output pulse width is determined by the capacitor C1, a differential pulse with a time constant determined by the resistor R1, and the threshold level of the circuit. Since a differential pulse having a polarity opposite to the differential pulse at the leading edge is generated at the trailing edge, the voltage at the connection point at each leading edge of the output pulse is not constant due to the frequency change of the FM signal. As a result, the output pulse width becomes inconsistent and demodulation distortion occurs.
例えば、FM信号をf(t)=f□ +△f cosp
tとすると、第2図の各部における信号波形はcosp
t =lの場合第4図のように、またcosptニー1
の場合第5図のようになり、Dの出力パルス幅が変化す
るわけである。For example, if the FM signal is f(t)=f□+△f cosp
t, the signal waveform at each part in Fig. 2 is cosp
When t = l, as shown in Fig. 4, cospt knee 1
In this case, the output pulse width of D changes as shown in FIG.
そこで、このような復調歪を改善するには単安定マルチ
バイブレークの時定数を小さくして出力パルス幅を小さ
くすれば良いが、そうすると復調出力のレベルが小さく
なってS/Nが悪化する。Therefore, in order to improve such demodulation distortion, the time constant of the monostable multi-bi break can be made smaller to make the output pulse width smaller, but if this is done, the level of the demodulated output becomes smaller and the S/N ratio deteriorates.
また、逆にS/′Nを良くするために単安定マルチバイ
ブレークの時定数を大きくすると復調歪が増加すること
になってしまう。On the other hand, if the time constant of the monostable multi-bi break is increased in order to improve the S/'N, demodulation distortion will increase.
本発明は上記欠点を解決して復調歪及びS/Nを共に改
善したFM信号のパルスカウント方式復調装置を提供す
ることを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a pulse count type demodulator for FM signals that solves the above-mentioned drawbacks and improves both demodulation distortion and S/N.
第3図は本発明の一実施例を示すブロックダイヤグラム
で、特にパルス変換回路3の構成を改良したものであり
、その他の構成は第1図と同じである。FIG. 3 is a block diagram showing one embodiment of the present invention, in which the configuration of the pulse conversion circuit 3 is particularly improved, and the other configurations are the same as in FIG. 1.
第6図は第3図の各部における信号波形図である。FIG. 6 is a signal waveform diagram at each part of FIG. 3.
第3図において、パルス変換回路3は縦続接続された2
つの単安定マルチバイブレーク6゜7と、この単安定マ
ルチバイブレーク6.7の各出力パルスの論理和を得る
論理演算素子8とで構成される。In FIG. 3, the pulse conversion circuit 3 has two cascade-connected
It is composed of two monostable multi-bi breaks 6.7 and a logic operation element 8 which obtains the logical sum of each output pulse of the monostable multi-bi breaks 6.7.
入力端子1に印加されたFM信号は、リミッタ回路2で
振幅制限されて第6図Eのパルス信号となり単安定マル
チバイブレーク6に印加される。The FM signal applied to the input terminal 1 is amplitude limited by the limiter circuit 2 to become a pulse signal as shown in FIG.
単安定マルチバイブレーク6は第6図Eのパルス信号の
前縁で動作し、第6図F、Gに示すようにコンデンサC
2及び抵抗R2による時定数で決まる幅T1の出力パル
スがQ、Q端子に得られる。The monostable multi-bi break 6 operates at the leading edge of the pulse signal shown in Figure 6E, and the capacitor C is connected as shown in Figures 6F and G.
An output pulse having a width T1 determined by the time constant of the resistor R2 and the resistor R2 is obtained at the Q and Q terminals.
単安定マルチバイブレーク7は単安定マルチバイブレー
ク6のQ出力の後縁で動作し、第6図Hに示すようにコ
ンデンサC3及び抵抗R3による時定数で決まる幅T2
の出力パルスがQ端子に得られる。The monostable multi-bi break 7 operates at the trailing edge of the Q output of the monostable multi-bi break 6, and has a width T2 determined by the time constant of the capacitor C3 and resistor R3, as shown in FIG. 6H.
An output pulse of is obtained at the Q terminal.
そこで、単安定マルチバイブレーク7の出力パルスと単
安定マルチバイブレーク6の出力パルスを入力信号の論
理和を得る論理演算素子例えばNAND8に印加すれば
、その出力に前記2つの出力パルス幅T1及びT2の和
の一定幅T3を有する第6図Iの出力パルスが得られる
。Therefore, if the output pulse of the monostable multi-bi break 7 and the output pulse of the monostable multi-bi break 6 are applied to a logic operation element, for example, NAND 8, which obtains the logical sum of the input signals, the output pulse has the width of the two output pulses T1 and T2. The output pulse of FIG. 6I having a constant width T3 of the sum is obtained.
論理演算素子8よりの出力パルスはローパスフィルタ等
の積分回路4で積分され、出力端子5にオーディオ信号
が得られる。The output pulse from the logical operation element 8 is integrated by an integrating circuit 4 such as a low-pass filter, and an audio signal is obtained at an output terminal 5.
すなわち、パルス変換回路3に複数個の単安定マルチバ
イブレータを用い、それらの各出力パルス幅の和の幅の
出力パルスを得るようにしたので、各単安定マルチバイ
ブレークの時定数を小さくすることができ復調歪が改善
される。That is, since a plurality of monostable multivibrators are used in the pulse conversion circuit 3 and an output pulse with a width equal to the sum of their respective output pulse widths is obtained, the time constant of each monostable multivibrator can be made small. demodulation distortion is improved.
また、時定数を大きくせずに単安定マルチバイブレーク
の個数を増せば希望する積分するべきパルス幅が得られ
るので、S/Nも改善することができる。Further, by increasing the number of monostable multi-bi-breaks without increasing the time constant, a desired pulse width to be integrated can be obtained, and the S/N can also be improved.
なお、論理演算素子8は上記実施例のNANDに限らず
入力信号の論理和が得られるものであればどのようなも
のでも良い。Note that the logical operation element 8 is not limited to the NAND of the above embodiment, but may be any type as long as it can obtain the logical sum of input signals.
また、各単安定マルチバイブレークに動作時間遅れがあ
る場合には、各出力パルスの前縁と後縁が一致するよう
にインバータ等を用いた遅延回路で各出力パルスを遅延
させてから論理和をとれば良い。In addition, if each monostable multi-bi break has an operation time delay, each output pulse is delayed by a delay circuit using an inverter etc. so that the leading and trailing edges of each output pulse match, and then the logical sum is performed. Just take it.
以上述べたように、本発明によればパルスカウント方式
復調装置におけるパルス変換回路に複数個の単安定マル
チバイブレークを用い、それらの出力パルス幅の和の一
定幅の出力パルスを得るようにしたので、従来の1個の
単安定マルチバイブレークを用いた場合の相反する条件
であった復調歪とS/Nを共に改善することができる効
果がある。As described above, according to the present invention, a plurality of monostable multi-by-breaks are used in the pulse conversion circuit of a pulse count type demodulator, and an output pulse with a constant width is obtained by adding the output pulse widths of the monostable multi-by-breaks. , it is possible to improve both demodulation distortion and S/N, which were contradictory conditions when using one conventional monostable multi-by-break.
第1図は従来のFM信号のパルスカウント方式復調装置
のブロックダイヤグラム、第2図は第1図におけるパル
ス変換回路の一例、第3図は本発明の一実施例を示すブ
ロックダイヤグラム、第4図及び第5図は第2図の各部
における信号波形図、第6図は第3図の各部における信
号波形図である。
1・・・・・・入力端子、2・・・・・・リミッタ回路
、3・・・・・・パルス変換回路、4・・・・・・積分
回路、5・・・・・・出力端子、6,7・・・・・・単
安定マルチバイブレータ、8・・・・・・論理演算素子
。FIG. 1 is a block diagram of a conventional FM signal pulse count demodulator, FIG. 2 is an example of the pulse conversion circuit in FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a signal waveform diagram at each part in FIG. 2, and FIG. 6 is a signal waveform diagram at each part in FIG. 3. 1...Input terminal, 2...Limiter circuit, 3...Pulse conversion circuit, 4...Integrator circuit, 5...Output terminal , 6, 7... Monostable multivibrator, 8... Logical operation element.
Claims (1)
分回路を経てオーディオ信号に復調するパルスカウント
方式復調装置において、前記パルス変換回路を、各々の
出力パルスの後縁で次段が動作し、FM信号の周波数変
移に対し出力パルス幅の変化を無視しうるだけ充分時定
数の小さい縦続接続された複数個の単安定マルチバイブ
レークと、前記各々の単安定マルチバイブレークの出力
パルスの論理和を得る論理演算素子とで構成し、前記リ
ミッタ回路の出力を前記各々の単安定マルチバイブレー
クの出力パルスを論理和した幅広のパルスに変換するよ
うにしたことを特徴とするFM信号のパルスカウント方
式復調装置。In a pulse count demodulation device that demodulates an I FM signal into an audio signal via a limiter circuit, a pulse conversion circuit, and an integration circuit, the pulse conversion circuit is operated at the trailing edge of each output pulse in the next stage, and the FM signal is A logical operation for obtaining the logical sum of a plurality of cascaded monostable multi-bi breaks whose time constant is sufficiently small to ignore changes in the output pulse width with respect to frequency changes, and the output pulses of each of the monostable multi-bi breaks. 1. A pulse count type demodulator for an FM signal, characterized in that the output of the limiter circuit is converted into a wide pulse obtained by ORing the output pulses of each of the monostable multi-bibreaks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50123534A JPS5855684B2 (en) | 1975-10-14 | 1975-10-14 | FM signal pulse count demodulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50123534A JPS5855684B2 (en) | 1975-10-14 | 1975-10-14 | FM signal pulse count demodulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5247362A JPS5247362A (en) | 1977-04-15 |
| JPS5855684B2 true JPS5855684B2 (en) | 1983-12-10 |
Family
ID=14862977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50123534A Expired JPS5855684B2 (en) | 1975-10-14 | 1975-10-14 | FM signal pulse count demodulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5855684B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5922755A (en) * | 1982-07-30 | 1984-02-06 | Komori Printing Mach Co Ltd | Plate holding device for sheet-fed rotary printing presses |
| JPH0773166B2 (en) * | 1988-09-28 | 1995-08-02 | 安藤電気株式会社 | Transient elimination circuit for pulse count detector |
| JPH02134903A (en) * | 1988-11-15 | 1990-05-23 | Nec Corp | Fm demodulating circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5327109B2 (en) * | 1973-11-27 | 1978-08-05 |
-
1975
- 1975-10-14 JP JP50123534A patent/JPS5855684B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5247362A (en) | 1977-04-15 |
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