JPS5855708B2 - phase demodulator - Google Patents

Description

[Detailed Description of the Invention] This invention provides a method for detecting the phase when a digital code such as a PCM code is transmitted in pulses by phase modulation and the phase is detected in various modes (for example, when the bit rate, detection method, etc. are different γ). It concerns a demodulator.

BACKGROUND ART In recent years, pulse transmission of digital codes by phase modulation has been frequently used in communication equipment and measurement equipment in fields such as satellite communication and terrestrial microwave communication.

The quality of pulse transmission of digital codes by phase modulation is defined by the code error rate, which is how faithfully the digital codes can be transmitted without errors, whereas analog signals are defined by the amount of noise.

The code error rate can be determined quantitatively if the ratio of the signal level S to the noise level N, that is, the S/N, is given, but in actual equipment, due to imperfections in the equipment, the code is determined by the S/N. worse than the error rate.

There are various causes of deterioration of the bit error rate due to imperfections in this equipment, but DC level drift of demodulated pulses is a particularly large factor, and reducing this DC level drift improves the performance of the equipment. It has also become

A conventional device of this type is shown in FIG.

In FIG. 1, 1a is an a-mode phase detection circuit;
1b is a phase detection circuit in b mode and a phase detection circuit in IXtzX mode.

Each mode shown above represents one of the combinations of different bit rates and detection methods, and one of the demodulated pulse trains demodulated by these phase detection circuits 1a to 1x is selected by the selection switching circuit 2 and the low frequency The signal is filtered by the wave circuit and baseband pulse amplification circuit 3 for effective pulse transmission, and amplified to a level necessary for code identification.

This output is subjected to waveform shaping and timing in a code recognition/reproduction circuit 4, and a differential phase modulated pulse train is decoded in a differential decoding circuit 5.

The timing waves necessary for the circuit operations of the code identification and regeneration circuit 4 and the differential decoding four-way 5 are extracted and regenerated from the power spectrum of the demodulated pulse train by a timing wave regeneration circuit 6 by nonlinear operation, and the timing waves are extracted and regenerated by the phase shifters 7 and 8 from the power spectrum of the demodulated pulse train. The waves are phased and supplied.

In conventional devices of this type, individual hardware such as phase detection circuits and baseband pulse amplification circuits were designed to have as little DC drift as possible, but this amount was also limited and could not be eliminated.

Additionally, if the bit speed or detection method differs, the method of generating the original pulse signal also differs, so the DC level of the phase-detected demodulated pulse varies greatly, and with conventional equipment, it must be manually adjusted each time. However, it has the disadvantage that it becomes unusable due to the difference in code error rate multiplied by the difference.

This invention was made to eliminate these drawbacks, and it regenerates the DC level from the phase-detected demodulated pulse, and automatically adjusts the DC level of the demodulated pulse to a constant value using the regenerated DC level. Since it has an automatic level control loop, even if the DC level of the demodulated pulse changes significantly due to different bit speeds or detection methods, the loop constant design automatically compresses the DC level drift and maintains the code. The present invention provides a phase demodulator that can significantly improve error rate degradation.

Hereinafter, one embodiment of the present invention will be described in detail using FIG. 2.

In FIG. 2, the same or corresponding parts as those in FIG. 1 are designated by the same reference numerals.

9 to 12 are parts added to the conventional circuit shown in FIG. 1, and in combination with the code identification and reproduction circuit 4 constitute an automatic level control loop.

Reference numeral 9 denotes a sampling pulse generation circuit, which generates sampling pulses from the output of the code identification/reproduction circuit 4 through logical processing.

That is, an N-stage shift register is provided, and when an arbitrary pulse pattern is achieved, a narrow sampling pulse is generated in the time slot in the middle.

In this case, the sampling pulse generation circuit 9 outputs the output from the code identification and regeneration circuit 4 in parallel while delaying it one bit at a time using a shift register, and also outputs the output from the code identification and regeneration circuit 4 in parallel, and the adjacent time slots differ from the pulse pattern output in parallel. It also has a function to determine whether it is a code or not.

In the time chart shown in FIG. 3, which shows an embodiment of the present invention, a three-stage shift register is provided to monitor a three-bit pulse pattern. (mark level)
The sampling pulse of ``0'' level (space level) is generated when the adjacent time slot is '0'' (space), and the sampling pulse of ``0'' level (space level) is generated when the adjacent time slot is 11'' (mark). .

The reason why we chose the case where adjacent time slots have opposite signs is that in this case, the power spectrum of the pulse pattern is the widest, the wave-dissipation effect is the greatest, and the influence of DC level drift on bit error rate deterioration is greatest. be.

The two types of sampling pulses generated here are sent to the pulse level detection circuit 10, and the 11" level (mark level) and the
〃The level (space level) is sampled and held, and the pulse level is detected.

'1' level (mark level) and XXO level (
Space level) sampling is performed only when a specific pattern occurs, so sampling pulses are generated randomly in PCM pulse trains, etc., but by appropriately selecting the time constant of the sampling holding circuit, the pulse level due to the pattern effect can be adjusted. Detection errors can be eliminated.

Since the phase of the sampling pulse from the sampling pulse generation circuit 9 lags behind the demodulation pulse from the DC level shift circuit 12, the phase between them is adjusted at the input section of the pulse level detection circuit 10.

Detected '1' level (mark level) 10'
The level (space level) is sent to the DC level regeneration circuit 11, where the DC level is regenerated through a low frequency original wave circuit and a DC level amplification circuit so as to have a time constant necessary for the response of the automatic level control loop.

The regenerated DC level is passed through a DC level shift circuit 1 in order to cancel out and reduce fluctuations in the DC level of the demodulated pulse.
Sent to 2.

Figure 3 shows the output waveforms of each circuit in Figure 2,
a is the output of the circuit 12 without the circuit according to the present invention, that is, when the automatic level control loop is OFF; b is the output of the circuit 12 with the circuit according to the present invention, that is, when the automatic level control loop is ON; C is the output of circuit 4 which has been discriminated and reproduced, and d and e are the sampling pulse of '1' level (mark level) and the sampling pulse of 'O' level (space level), both of which are outputs of circuit 9. , f2g
are respectively 11" level (mark level) oyohiゝ0〃
The output of the circuit 10 detected by sampling and holding the level (space level), h is the output of the circuit 11 at the reproduced DC level.

FIG. 4 shows the operation of the DC level shift circuit 12 shown in FIG. 2. The solid line shows the input response during normal operation, the broken line shows the input/output response when the DC level of the input pulse increases, and the dashed line shows the input/output response when the DC level of the input pulse increases. There is an input/output response when the DC level of the input pulse drops.

In other words, when the DC level of the input pulse increases, circuits 9 to 1
Since the DC level reproduced in step 1 also increases, if this is added to the base of a grounded base amplifier circuit, for example, the input/output characteristics will shift to the right as shown by the broken line, and as a result, the DC level of the output pulse will be lower than normal. approach the case response.

Also, when the direct current level of the human pulse decreases, the same operation as above is performed.

Therefore, if the deviation amount and deviation speed of the DC level of the human pulse are given, the DC level of the output pulse can be kept close to constant by appropriately selecting the time constant of the automatic level control loop.

The code error rate when the DC level of the demodulated pulse changes and deviates by α from the optimum threshold value of the code discriminator is theoretically given by the following equation.

Here, [P; demodulated pulse train mark rate, Pa3) n
S: Insertion code error rate (%0//1%1"), Pa
, omi; Erasure code error rate (″1″→″′0″)
, n; Noise effective value/maximum signal wave peak value, α; (DC level deviation) x 27 signal wave maximum peak value, PI(n);
Ideal transmission system code error rate with only noise n, Φ(t); error function] In actual equipment, the deterioration of the code error rate due to the DC level fluctuation t of the demodulated pulse must be kept below 1.0 dB; It is necessary to set α to 0.1 or less.

This value is a value that is extremely difficult to achieve when considering long-term temperature fluctuations and power supply fluctuations, even when using a phase detection circuit in one mode of any of circuits 1a to 1x. The difference in the DC level of the demodulated pulse between the input and output of the circuits 13 to 1X is α of 0.2 or more, and it is extremely difficult to operate in any mode without adjustment. It becomes necessary.

Although the above description has been made regarding the case where digital codes are transmitted using a phase modulation method, this invention is not limited to this, and even when baseband transmission is performed using a coaxial cable, etc., the present invention is applicable to the case where digital codes are transmitted using a phase modulation method. It is possible to compensate for a large DC level shift and improve the deterioration of the bit error rate.

As described above, since the phase demodulator according to the present invention has an automatic level control loop with negative feedback, it can be operated without adjustment by selecting the loop constant, no matter how much the DC level of the phase-detected demodulated pulse changes. It has the great effect of being able to

Further, when the phase demodulator according to the present invention is used with the loop OFF, the phase axis of the phase detection circuit can be easily set, and the device can be easily adjusted.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing a conventional phase demodulator, FIG. 2 is a system diagram showing an embodiment according to the present invention, FIG. 3 is a time chart showing circuit operation according to the embodiment shown in FIG. FIG. 4 is a conceptual diagram of the operation of the DC level shift circuit shown in FIG. 2. In the figure, 1a to 1x are phase detection circuits, 2 is a selection switching circuit, 3 is a low frequency dissipation circuit and a baseband pulse amplification circuit, 4 is a code recognition/regeneration circuit, 5 is a differential decoding circuit, and 6 is a timing waveform. A reproduction circuit, 7.8 is a phase shifter, 9 is a sampling pulse generation circuit, 10 is a pulse level detection circuit, 11 is a DC level reproduction circuit, and 12 is a DC level shift circuit. In the drawings, the same or corresponding parts are designated by the same reference numerals.

Claims (1)

[Claims] 1. In a digital code phase demodulator, a sampling pulse generation circuit generates a sampling pulse in the middle time slot of a pulse pattern when adjacent time slots have different codes from a phase-detected pulse signal; 11” level of sign (mark level) and % 0
//A pulse level detection circuit that samples and holds and detects the level (space level) using the sampling pulse, and the '1〃 level (mark level) and 10'' level (of the pulse detected by this pulse level detection circuit). A DC level regeneration circuit that generates a DC level from the DC level (space level), and a DC level shift circuit that shifts the phase-detected pulse 0 DC level by the DC level regenerated by the DC level regeneration circuit, A phase demodulator that compensates the DC level of phase-detected pulses in a self-ttJJ manner.