JPS5858633B2 - antenna pattern generator - Google Patents

Description

[Detailed Description of the Invention] The present invention simulates and generates signal voltage fluctuations corresponding to fluctuations in electric field strength caused by spatial deviation of the directivity of an antenna pattern sweeping through space. The present invention relates to an antenna pattern generator.

For example, as shown in Fig. 1, when the radar tower 1 actually conducts a radar search, the directivity 2 of the radar antenna on the head of the radar tower 1 indicates that the radar is operating in search mode. When there is a dotted line, the line is repeatedly swept between dotted line 3 (dotted line AB) and dotted line 4 (dotted line AC) in a plane parallel to the plane of the paper.

Here, it is assumed that the target 5 is I above the solid line 6 (solid line AE) drawn from the radar antenna position A, and ZEABθ1, Z
When the EAC is θ2, the target 5 is in a direction shifted by an angle θ2-01 from the axis T (dotted chain line AD) of the radar tower 1.

Here, it is assumed below that θ2≧θ1.

In the opposite case, the symbol for the larger angle can be changed to 02.

In this case, if a receiver for reverse search is mounted on the target 5 and receives the radar radio waves, the level of the received signal changes in amplitude in accordance with the antenna pattern.

To test, adjust, etc. the above-mentioned receiver, it is necessary to simulate in real time the level fluctuations of the radar signal caused by the spatial sweep of the antenna pattern in a circuit. requires an antenna pattern generator.

Conventionally, in order to simulate and generate an antenna pattern circuit-wise in real time, extensive electronic equipment including a medium-sized or higher-speed computer is required, and the operating location, operating personnel,
The required cost and other factors have been a major constraint, significantly hindering its use in normal experimental work.

In view of the above points, the present invention stores one side of a left-right symmetrical antenna pattern from the main axis in FROM#, and sets two angles θ1... set by a digital switch. The digital values of θ2 and angle 0° are compared with the digital value of the output of the up-down counter, and when they match, the up-down counter is reversed and the set angle θ1. θ2
At the smaller setting angle θ1, a ternary counter is used to count two out of three times as is without reversing, thereby generating an analog voltage corresponding to the antenna pattern stored in the FROM. By doing so, it is an object of the present invention to provide a real-time simulated antenna pattern generator that is small and lightweight, can be operated at any location without being limited, and can respond at high speed at a low cost.

Next, an embodiment of the apparatus according to the present invention will be described with reference to the drawings.

FIG. 2 shows a circuit diagram of an antenna pattern generator according to the present invention.

The target antenna pattern is stored in FROM8, but since the directivity of the radar antenna is often symmetrical about the main axis, as shown in Figure 3, the required angular range on only one side from the main axis is It is sufficient to memorize the value of .

As a result, the storage capacity of the FROM 8 can be saved in half, and conversely, if the storage capacity is constant, sampling of the antenna pattern to be stored can be performed twice as precisely.

Angle θ indicating the sweep range of the antenna pattern shown in Figure 1
1. θ2 is set to digital switches 9° and 10, respectively.

The digital output of digital switches 9 and 10 is FROM8
The comparators 12 and 1 are compared with the digital output of the up/down counter 11 that drives the address bus of
3, respectively.

The output of the comparator 12 of the digital switch 9 system where θ1 is set enters the ternary counter 14.

On the other hand, in order to detect the angle O0, a comparator 15 that compares the digital value of the angle O0 and the output of the up/down counter 11 is connected to the address on the output side of the up/down counter 11.

The outputs of comparators 13, 15 and ternary counter 14 enter OR gate 16, and the output of OR gate 116 is connected to latch circuit 11.

The output of the latch circuit 11 is connected to the up/down control terminal of the up/down counter 11, and up/down counting of the up/down counter 11 is controlled depending on the state of the latch.

Further, the output of the clock signal generator 18 is connected to a terminal for controlling the counting speed of the up/down counter 11.

The output of the FROM 8 is converted to an analog voltage by a D/A converter 19, amplified by an amplifier 20, and supplied to an output terminal 21, so that voltage or power corresponding to the antenna pattern can be extracted.

The reset switch 22 simultaneously resets the ternary counter 14, the latch circuit 11, and the up/down counter 11.

To explain the operation of the device according to the present invention described above, first, the reset switch 22 resets the address of FROM 8 to the angle O0.

Next, when the output of the clock signal generator 18 is added to the up/down counter IH, the counter 11 starts counting up the address.

This is shown in Figure 4. As the address counts up (increases), the antenna sweep angle θ (the angle formed by the main axis AP of the antenna beam and AE in the target direction in Figure 1) increases (this changes, so θ increases linearly with increasing time t.

When θ2 θ1 (point g in the figure), ternary counter 14
stores a count of 1.

Further, θ increases, and when θ=θ2, an output appears in the comparator 13, passes through the OR gate 16, inverts the state of the latch circuit 1γ, and causes the up/down counter 11 to count down.

Therefore, in FIG. 4, θ decreases as time t increases, and changes along the straight line ab in the figure.

When θ2θ1 (point h in Figure 4), the ternary counter 1
4 stores count 2.

When the value θ decreases to θ=00, a signal appears on the output side of the comparator 15, which inverts the state of the latch 11 via the OR gate 16 and causes the up/down counter 11 to invert the state of the latch 11.
to up count.

θf starts to increase again and changes along the straight line bc in FIG.

When θθ1 (point C in the figure) is reached, the ternary counter 14 stores a count of 3, resets itself, and sends a signal to the output side.

This inverts the state of the latch 11 through the OR gate 16 and causes the up/down counter 11 to count down (rubbing).

Thereafter, the same process is repeated, and by the action of the ternary counter 14, the change in θ alternates between θ2 and θ2, as shown in FIG. It turns around at θ1 (on the time axis, the angle θ1 is shown in Figure 5).
．． Voltages corresponding to the four antenna patterns alternately folded back at θ2 are obtained.

This waveform exactly corresponds to the electric field strength of the radar radio wave received by the target aircraft 5 in FIG. 1, and it can be seen that the present device has the function of achieving the intended purpose.

As described above, the present invention stores one side of a left-right symmetrical antenna pattern from the main axis in the FROM, and stores two angles θ1°θ2 and O0 set by a digital switch.
The digital value of the up-down counter is compared with the digital value of the output of the up-down counter, and when they match, the up-down counter is reversed and the set angle θ1. In the setting angle θ11, which is the smaller of θ2, a ternary counter is used to count 3 times and 2 times without reversing, and the analog voltage corresponding to the antenna pattern stored in the above FROM is calculated. Since the structure generates the antenna pattern, it is possible to provide an antenna pattern generating device that is small and lightweight, and can perform real-time simulation at high speed.

Also, in the present invention, FROM may be added or FROM may be added.
If the ROM is configured to be replaceable, various antenna patterns can be generated efficiently, easily, and with high precision, making it highly practical and can be used effectively for testing various radar receivers. be.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing the positional relationship between the antenna and the target when the antenna pattern is generated, Fig. 2 is a block diagram showing the circuit system of the present invention, and Fig. 3 is a characteristic curve showing an example of the antenna pattern stored in FROM. 4 is a characteristic curve diagram showing the relationship between time and antenna pattern sweep angle, and FIG. 5 is a characteristic curve diagram showing an example of the output waveform of the device according to the fourth aspect of the present invention. 8...PROM, 9.10...Digital switch, 11...Up/down counter,
12, 13°15... Comparator, 14.
...Ternary counter, 16...OR gate, 17...Latch circuit, 18...Clock signal generator, 19...D/ A converter, 20
······amplifier.

Claims (1)

[Claims] 1. A FROM that stores one side from the main axis of a symmetrical antenna pattern, an up/down counter that drives the address of this FROM, and outputs the digital values of the two angles set by two digital switches from the up/down counter. and one comparator to compare the digital value of the angle O0 with the output of the up/down counter; three comparators, and the value of the smaller or equal angle of the two angles. A ternary counter driven by the output of a comparator connected to the digital switch to be set, an OR gate that takes the logical sum of the output of this ternary counter and the outputs of the remaining two comparators, and this OR gate. a latch circuit that temporarily holds the output of the FROM, a D/A converter that converts the output of the FROM, an amplifier that amplifies the analog output of the D/A converter, and the ternary counter and launch circuit. It is equipped with a reset switch that simultaneously resets the up-down counter, and when the two angles set with the digital switch and the digital value of the angle O0 match the digital f value of the output of the up-down counter, the angle O0 and the two set angles are reset. For the larger or equal set angle, the up/down counter is counted up or down once in three times by the operation of the ternary counter for the remaining smaller or equal set angle. An antenna pattern generation device characterized in that the direction of countdown is reversed and an analog voltage corresponding to an antenna pattern stored in a PROMI is generated.