JPS5858856B2 - oscillation device - Google Patents

Description

[Detailed description of the invention] The present invention relates to parallel redundant oscillators.

For example, in an inverter device used as an uninterruptible power source, it is common to operate a plurality of inverters connected in parallel for the purpose of improving reliability as a power supply system.

However, in this case, the oscillator that serves as the frequency reference for the parallel system of inverters is provided in common for each inverter, and if this common oscillator fails, all inverters will be unable to operate. The reliability of the system determines the reliability of the system.

Conventionally, methods for improving the reliability of oscillators include:
A so-called standby redundancy system has been considered in which a plurality of oscillators are prepared, one arbitrary oscillator is selected, and when this oscillator fails, the oscillator is switched to another healthy oscillator in a standby state.

FIG. 1 is a block diagram of a conventional device using this standby redundancy system.

In the figure, 1, 2.3 are inverters that are operated in parallel to supply AC power to the load, and 10, 20.30 are always operated and the output of any one unit is selected by a selection switch IL21.31. Each oscillator 41, which commonly supplies frequency reference pulses to inverters 1, 2.3, detects an open phase in the selected oscillator output to detect an oscillator failure, and by operating a selection switch, the reference pulse is set to be healthier than the failed oscillator. This is a pulse phase loss detection circuit that switches to the oscillator.

However, this method has conventionally had the following drawbacks.

(1) The reliability of the pulse open phase detection circuit becomes a problem.

(2) Reliability of the selection switch becomes a problem.

(3) At the time of switching, there is a blank period in which there is no oscillation output, and this blank period becomes longer as the number of oscillators prepared increases, and the operation of the inverter during this period becomes a problem.

(4) Unless all inverters are stopped, maintenance and inspection of the entire common oscillator, such as the pulse loss detection circuit and selection switch, is impossible.

(5) As the number of oscillators prepared increases, the interlocking between the selection switches to prevent two or more oscillators from being selected at the same time becomes more complex.

The present invention has been made in view of the above points, and an object of the present invention is to provide a highly reliable oscillation device that eliminates the above conventional drawbacks without providing a pulse open phase detection circuit and a selection switch. do.

An embodiment of the present invention will be described below with reference to FIG.

In the figure, the oscillation device is an oscillation circuit IA. It consists of 2A and 3A, and the oscillation circuit IA and 2A.

A frequency-based pulse is given to each inverter 1.2.3 operated in parallel from a signal line (hereinafter referred to as a common bus) that commonly connects the 3A output.

The oscillation circuits IA, 2A, and 3A have the same configuration, so
To explain the circuit 1A as a representative, 101 is an oscillator whose oscillation frequency is N times that of the reference oscillator 10 in FIG.
2 is the reference pulse 10i output by the oscillator 101 as 1, 2...
・The count is reset at the Nth pulse, and a divided output pulse is generated, and the output 1 of the AND circuit 15 is
This is a 1/N frequency divider with an external reset that generates a pulse similar to the above-mentioned frequency divided output by being reset by using an external reset command to 0. An example of the specific circuit is shown in Figure 4. shown.

In addition, 13.14 is a monostable multi-bi break that generates an output pulse of a constant width each time an input is input, and 16 is a monostable multi-bi break that generates a pulse 101\ generated by the monostable multi-bi break 13. The line driver 17 is a line receiver that receives a signal pulse on the common bus and supplies it as a trigger pulse to the monostable multivibrator 14. An example of the circuit is shown in FIG.

An example of the frequency divider 12 with external reset is a binary synchronous counter 311 of a predetermined bit as shown in FIG.
, the output of the 2n stages of the binary synchronous counter 311 is logically summed with the external reset command, and the clear input of the binary synchronous counter 311 is set to 2°, 21
．． - When the OR circuit 312 gives a reset command so that the outputs of each stage of 2 n are all "0", and the binary synchronous counter 311 is reset, 2°, 21 . . . 2
When all the outputs of each stage of n become “Ott”, 1 out of 10
'', and the frequency division ratio is selected to be N=2H.

In other words, the binary synchronous counter 311 normally operates as an N-ary counter that counts the human input 10 as a clock, and outputs "1" to the output 10 during carry operation, and when a reset command is given to the external reset input 10. If it is, “1” will be sent to output 10, as in the case of carry operation.
``The output is sent out, and the N-ary counter is reset and starts counting 1, 2, and so on again.

FIG. 5 shows an example of the combination 1B of the line driver 16 and line receiver 17, in which 314 to 316 are resistors;
17 is a capacitor, 318 is a transistor, 319 is a diode, and 320 is a pulse transformer.

Vcc is a power supply, and COM is a ground potential.

When 1<I I+ is applied to the input terminal 10 of the line driver, the charge of the capacitor 317 is transferred to the transistor 31.
8 turns on, discharging occurs through the transistor 318 and the primary winding of the pulse transformer 320.

At this time, the voltage of the capacitor applied to the primary winding of the pulse transformer 320 is applied to the pulse transformer 320 as a pulse.
Is it transmitted to the secondary winding of 0? A pulse appears at the output terminal 102 of the common bus and line receiver.

Furthermore, even if the input terminal 10 of the line driver is "0", if a pulse from another oscillation circuit is applied to the common bus, this pulse is transmitted through the pulse transformer 320 and the output terminal of the line receiver A pulse appears on 102.

Next, the operation of the above configuration will be explained.

FIG. 3 shows a time chart of the embodiment shown in FIG.

In the figure, the symbols 10A to 10, 20B to 20A, and A correspond to the respective parts of the embodiment shown in FIG.

As shown in the figure, if the output pulse 10i of the oscillator 101 is ahead of the output pulse 20i of the oscillator 201 by Ta2 in phase, the signal A appearing on the common bus is
The oscillation circuit 2 is determined by one oscillation circuit including the oscillator 101, and the oscillation circuit 2 operates by apparently moving in accordance with the signal A on the common bus determined by the one oscillation circuit.

To explain the details of its operation, the square frequency divider 12 counts N output pulses 10 of the oscillator 101 and performs a 1/N frequency division operation to output "1" like 10 bits. The 10 frequency-divided outputs are given to the monostable multi-bi break 13, and the pulse width T32 is
is converted into a pulse of and passes through the line driver 16,
Sent to Common Bathy.

At the same time, the signal A on the common bus is given to the monostable multi-by break 14 through the line receiver 17, as shown in 102, and converted into a pulse 10 ho with a pulse width T33.
The AND of the Q output of the oscillator 101 and the output 10i of the oscillator 101 is
Since this is done by the D circuit 15, an external reset command for the frequency divider 12 does not appear at the output 10 of the AND circuit 15.

On the other hand, for the two oscillator circuits, the signal A on the common bus is
Similar to the IA, it is sent to the monostable multi-by break 24 through the line receiver 17, converted into a pulse such as 20 Ho, and sent to the Q output of the monostable multi-by break 23 and the output 20 of the oscillator 20. By taking the logical product of .

As explained in the specific example of FIG. 4, this frequency divider 22 outputs 1" at the 20 ports during the reset operation as well as during the frequency division operation, and the "1" output from the 20 ports is Through the monostable multi-by-break 23, it is converted into a pulse with a pulse width T32, such as 10H as well as 20H, and further sent through the line receiver 26 onto the common bus.

As a result, the pulse I on the common bus is 10 and 2 for a pulse width T320) of 10 or 20
The pulse has a pulse width of T3□+T31 with the addition of the phase difference T31 of 0i, and its period T2 is N times the period T1 of the pulse 10i0 output by the oscillator 101.

Here, the pulse width of the pulse on the common bus is T32+T
When considering 3□, T31 is represented by the oscillator with the largest phase difference among the plurality of oscillators with respect to the oscillator 101.

In addition, in order to prevent an external reset command from appearing at 10 or two consecutive external reset commands from appearing at 20, the pulse width of the pulses generated by the monostable multi-bi breaks 13 and 14 is set at T3゜〉T33. 〉The relationship is selected to be as shown in T1.

Next, the operation when the first oscillator 101 stops due to a failure or the like will be described.

When the 10th oscillator 101 stops at time t3□, the 1st oscillator 101 stops.
0) The frequency divider 12 of the oscillation circuit 1A stops the frequency division operation.

On the other hand, the two frequency dividers 22 of the second oscillator circuit continue to count the 20 pulses output by the second oscillator 201, and the reset command by the signal from the common bus is automatically set to 20. 1/N frequency division operation is started,
Similar to the single first oscillation circuit during normal operation, pulses are sent to the common bus through the monostable multi-bi break 23 and the line driver 26 as shown in A.

However, even if a signal appears on the common bus, oscillator 1
01 is stopped, the output 10 of the N (e) circuit 15
No reset command appears in , and the output of frequency divider 12 is “
It remains OF+.

The frequency difference at the time of transition from the first oscillator 101 to the second oscillator 201 increases by the phase difference T31 compared to the normal period T2 as shown in A, and becomes only T2,000 T3□. Phase difference T3. is T3. Since <T1, at least one of the frequencies becomes T2+T3 and <T2+T1.

Therefore, by selecting a large frequency division ratio N of the frequency divider 12, T2>T1 can be satisfied, and the frequency deviation can be made so small as to be almost negligible.

This frequency shift remains the same no matter how many oscillators you increase, so if you increase the number of oscillators as before,
Problems such as an increase in blank periods without oscillation output during switching do not occur.

In the above explanation, when the first oscillator 101 stops, the transition is made to the second oscillator 201. Priority will be given to the oscillator with the most advanced oscillator.

The Φ operation of the embodiment of the present invention has been described above, but according to the oscillation circuit as described above, the pulse phase loss detection circuit and selection switch in the conventional standby redundancy system do not need to be provided at all, so it is very effective. It is possible to realize a simple configuration and an extremely reliable oscillation system.

In addition, in the conventional standby redundancy system, two oscillators are activated simultaneously.
There is no need for complex interlocks between selection switches (the more oscillators there are, the more complicated they become) to prevent selection of more than one unit.According to the oscillation circuit described above, the number of oscillators No matter how many oscillation circuits are increased, the only interconnection between the oscillation circuits is the common bus line, especially the oscillation circuits IA and 2A according to this method.

If 3A is expanded to a system in which each inverter L2 and L3 operated in parallel is provided with one circuit, control signals can be sent and received between each inverter using only the common bus line, which is very simple. It can be configured as follows.

On the other hand, regarding maintenance and inspection of the oscillation circuits IA, 2A, and 3A, if at least one circuit is removed from these oscillation circuits, leaving at least one circuit remaining, the same operation as in the case of stopping oscillation described above will occur. Therefore, it is possible to perform maintenance and inspection on each circuit in turn, and the problem of conventional methods, where maintenance and inspection of the entire common oscillator cannot be performed unless all inverters are stopped, is eliminated. .

FIG. 6 shows another embodiment of the invention.

This is the oscillator 101 in the oscillation circuit 1A of the embodiment shown in FIG.
The parts other than 1 are duplicated for the purpose of further improving reliability, and the outputs of each line driver are logically multiplied by an AND circuit 161 and connected to a common bus.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional common oscillator, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is an operation waveform diagram for explaining the operation of the embodiment of FIG. 2, and FIG. The figure is a circuit diagram showing an example of a frequency divider used in the embodiment of FIG. 2, FIG. 5 is a circuit diagram showing an example of a combination of a line driver and a line receiver used in the embodiment of FIG. 2, and FIG. FIG. 2 is a block diagram showing another embodiment of the present invention. L2, 3... Inverter, 10, 20.30.
...Reference oscillator, IL2L31 ... Changeover switch, 41 ... Pulse phase loss detection circuit, 1
01... Reference oscillator, 12... Frequency divider, 13.14... Monostable multivi break,
15,161...AND circuit, 16...
・Line driver, 17...Line receiver.

Claims (1)

[Claims] 1. An oscillator, a frequency divider that divides the output of this oscillator, a line driver that receives the output of the frequency divider and sends out pulses to the output line, and receives a signal from the output line and gives a heliset command to the frequency divider. A plurality of oscillation circuits consisting of line receivers are installed, and their output lines are commonly connected as a common signal line, and the pulses sent from one oscillation circuit to the common signal line are used to divide the frequency in other oscillation circuits. A parallel redundant oscillation device characterized in that the devices are apparently synchronized, and when an oscillator in one oscillation circuit stops, pulses are automatically sent from another oscillation circuit onto the common signal line.