JPS586315B2 - Koumitsudohiseban - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring board, such as a printed wiring board, on which signal wiring patterns are wired at high density.

Typical conventional wiring boards are made by drilling through holes in a laminated board made of an insulating substrate covered with a metal conductor such as copper, plating the through holes with metal, and printing the desired wiring pattern. It consisted of a process of plating an etchable metal and finally forming a desired signal wiring pattern by selective etching.

According to such a conventional method for manufacturing a printed wiring board, it is necessary to first design a required signal wiring pattern and then create a master plate for manufacturing the wiring board from this pattern.

In the conventional manufacturing of these printed wiring boards, a large number of man-hours were required for designing and creating original plates.

In other words, when designing a wiring pattern, in conventional printed wiring boards, patterns are arranged on a two-dimensional plane. Since routing had to be performed within the wiring area, the degree of freedom in wiring was reduced and a large number of man-hours were required.

In recent years, as the density of wiring boards has increased, this pattern design has been automated using computers. It is divided into rated elements and routing processing is performed.

In order to increase the density of the wiring pattern in such automated design, it is necessary to reduce the value of the rating element and equivalently increase the allowable wiring area, but this requires an increase in the memory capacity of the computer. At the same time, there are manufacturing limitations, so it is not possible to expand the wiring area indefinitely.

On the other hand, the actual wiring pattern on the printed wiring board created by pattern design must be prepared as a photographic original for printing during the manufacturing process.

In order to create this original photo plate, it is necessary to create the original image automatically or manually, and use this as a master to perform photographic operations, etc., and the process from creating the original plate to taking the photo requires a large amount of man-hours. I needed it.

For this reason, as an alternative to the conventional printed wiring, there is a method for manufacturing an electrical connection body disclosed in Japanese Patent Publication No. 45-21434 as a method aiming at high density.

According to this method of manufacturing an electrical connection body, a metal wire covered with an insulator is wired on a catalytic substrate, a predetermined through hole is made, electroless plating is applied, and the metal wire and the through hole are electrically connected. is connected to.

In such electrical connections, whereas conventional printed wiring boards are limited to running wiring patterns on a two-dimensional plane, insulated metal wires are used to create a crossing structure. As a result, the degree of freedom in pattern design is increased, and the turnaround time from design to manufacturing can be shortened, such as by shortening design time, increasing wiring density, and shortening the time to create an original.

However, even in this method of manufacturing an electrical connection body, the following design difficulties remain when high-density wiring is attempted, as in the case of the conventional printed wiring board described above.

In other words, the automatic routing of the wiring pattern design using a computer is performed by assuming that the position of the through hole is on the rating element, and that the route through which the metal wire runs is on a quasi-rating element that is an integer fraction of the rating element. However, there were manufacturing limitations due to (1) the problem of a rapid increase in computer memory capacity, and (2) mechanical constraints when actually wiring metal wires and catalytic substrates. .

The object of the present invention is to improve the [method for manufacturing electrical wiring bodies] disclosed in Japanese Patent Publication No. 45-21434, and to improve the method for manufacturing electrical wiring bodies without increasing the memory capacity in automatic routing of wiring paths by computer. An object of the present invention is to provide a wiring board on which a wiring pattern can be designed and manufactured at a higher density than that of a circuit board.

That is, in the high-density wiring board of the present invention, the center of the through hole is located on the intersection of the rating elements, and the quasi-lattice that divides the rating element into two and the quasi-lattice on both sides of the rating element are smaller than 1/2 of the diameter of the through hole. It is characterized by selectively wiring signal lines on a virtual grid offset by a predetermined value.

Next, the features and effects of the present invention will be explained in detail by way of examples.

FIG. 1 shows one embodiment of a high-density wiring board according to the present invention.

In FIG. 1a, the through holes 4 are located on the intersection of the rating coordinate system indicated by the solid line 1, for example, at intervals of 2. It is located with a rating element of 5mm.

A solid line 1' represents a quasi-lattice coordinate system that bisects the rating element 1.

Moreover, the dotted line 2 and the dashed-dotted line 3 are virtual lattice coordinate systems offset from the center of the through-hole on the diagonal quadrant by a value smaller than 1/2 of the through-hole diameter.

For example, the virtual lattice coordinate system 2 includes the rating element 1 and the quasi-lattice 1'
The virtual grid 3 is also offset by -0.25 mm on the X axis and -0.25 mm on the Y axis, and the virtual grid 3 is also offset by +0.25 mm on the X axis and +0.25 mm on the Y axis.
It is offset to the axis +0.25mm.

FIG. 1b shows a state in which the through hole and the conductor of the metal wire are located in each of the three coordinate systems shown in FIG. 1a.

The electrical connections running in the virtual grid coordinate systems 2 and 3 are insulated electrical circuits similar to those shown in Japanese Patent Publication No. 45-21434, and can freely intersect on the same plane.

In conventional wiring methods, for example, when passing a 0.16 mm insulated electrical circuit through a grid interval of 2.5 mm through holes, 2.
In order to create fine grids with intervals of 1/2 and 1/4 of the 5 mm rating element, treat these fine grids as an independent grid system, and create a wiring pattern on them, an automatic design (routing) processing computer is used. All the coordinates on the fine grid had to be stored, resulting in an increase in storage capacity.

Furthermore, there is a drawback in that the wiring on the fine grid, especially the 1/4 fine grid, tends to short-circuit to lands provided around the through holes, making it difficult to increase the wiring density.

In the present invention, by using a virtual grid offset by a certain amount with respect to the rating element 1 passing through the through hole and the quasi-grid 1' bisecting the space between the rating elements, the coordinates on the virtual grid are independent. There is no need to memorize it, and it is sufficient to use the standard grid coordinate system (rater 1 and quasi-grid 1') and add the translation value (offset amount) of the virtual grid to it later, which increases the storage capacity as described above. In addition, the software can be simplified in terms of design automation.

Furthermore, since the virtual grid offset from the rating element 1 is always in contact with the through-hole, the wiring is designed so that it is always connected to the land of the through-hole.

On the other hand, since the virtual lattice offset from the quasi-lattice 1' is away from the through-holes, the drawback of wiring on the conventional 1/4 fine lattice, in which wiring and lands tend to short-circuit, is completely eliminated.

FIG. 1C is a sectional view taken along line A-A in FIG. 1B, and shows a high-density wiring board with a four-layer structure.

Electric conductors 5, 6 run through the first layer and the fourth layer;
A state in which the conductor 7 is located in the third layer is shown.

In the above embodiment, the offset virtual grids 2 and 3 were located on the same plane, whereas in another embodiment of the invention shown in FIG. 3 are located in different planes.

Figure 2 shows a cross-sectional view of such a high-density wiring board with a six-layer structure. The electrical conductor is the first
layer, located in the 6th layer.

Furthermore, both are insulated from each other with an insulator, similar to a normal multilayer printed wiring board.

According to this embodiment, the high density described in the first embodiment can be implemented more easily.

As described above, according to the embodiments of the present invention, the storage capacity of a computer required for automatic design such as design automation can be reduced, and the software can be simplified.

[Brief explanation of drawings]

FIG. 1a is a virtual grid coordinate system diagram of an embodiment of the present invention;
FIG. 1b shows an example of how an electric conductor runs on the coordinate system of FIG. 1a, FIG. 1C shows a sectional view of FIG. 1b, and FIG. 2 shows a sectional view of another embodiment of the present invention. 1... Rating element coordinate system where the through hole is located, 1'... Quasi-lattice coordinate system that bisects the rating element, 2, 3... From the rating element and quasi-lattice, the diameter of the through hole is smaller than 1/2 Virtual grid coordinate system offset to the value, 4...through hole, 5, 6...electric conductor, 7...inner layer conductor.

Claims (1)

[Claims] 1 The center of the through hole is located on the intersection of the rating elements, and a predetermined value smaller than 1/2 of the diameter of the through hole is provided on both sides of the quasi-lattice that bisects the area between the rating elements and the rating element. A high-density wiring board characterized in that signal wiring is selectively performed on an offset virtual grid.