JPS586431B2 - Teletext receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to signals related to characters, graphics, etc. (hereinafter referred to as character signals) that are multiplexed and transmitted in a part of the vertical blanking period of a television signal.

), stores it, and displays the readout output on a television screen.In particular, it is a character signal receiving device that receives a signal, stores it, and displays the readout output on a television screen.In particular, it is a character signal receiving device that receives a signal from a computer, stores it, and displays the readout output on a television screen. To provide a character signal receiving device which prevents the effect of this on the reproduction screen of character signals.

The phases of horizontal and vertical synchronization signals of television signals sent from a broadcasting station may shift at the timing of switching between a camera and a VTR, or between a local station and a central station.

When such a transmission signal is received, the character signals on the television screen may be distorted vertically, horizontally, or sometimes completely, resulting in an abnormal image each time the switching occurs.

In view of this point, it is an object of the present invention to provide a character signal receiving device that prevents image distortion.

Before explaining the embodiments of the present invention, an outline of a teletext receiver will first be explained.

A character signal sent superimposed on the vertical retrace period of a television signal, for example, 20H (U283H in the next field), is expressed as shown in FIG.

Here, S1 is called STX, and is useful for determining the start position of a character signal, and is used to set the timing of a clock or gate signal used for reading and reading signals.

S2 is the program code, consisting of 4 bits and 10 bits from the sending side.
Programs are sent using program codes.

S3 is a scanning line code, which consists of 8 bits and indicates which scanning line the character signal belongs to since character signals are sent for only one horizontal scanning line per field.

S4 is a character signal portion, consisting of 245 bits.

Characters are composed of 18 dots vertically and 15 bits horizontally, 16 characters per line (however, the last character is 4 bits horizontally)
, the character spacing is 1 bit, and the line start is 1 bit, so the horizontal direction is 245 bits.

Also, one screen is composed of 8 lines, and the line spacing is 8 bits, so the screen has 208 bits in the vertical direction.

In this way, the character signal portion S4 is displayed on the television screen as shown in FIG.

S5 is an H synchronization signal, and the character signal portion S4
1 bit of is 5/8fsc= 1 7 5 nS ,S
TXS. , program code S2 and scanning line code S4 are 5/4.
fsc-3 50 nS.

In addition, fsc:3, 579545MHZ.

S6//'i color burst.

A conventionally proposed configuration of a teletext receiving apparatus for receiving and displaying such character signals will be described with reference to FIG.

A television signal received by an antenna 1 is subjected to high frequency amplification, frequency conversion, intermediate frequency amplification, and video detection in a circuit 2 to obtain a video signal.

This video signal is supplied to a waveform shaping circuit 3, a sync separation circuit 4, and a color subcarrier recovery circuit 5.

The synchronization signal separated by the synchronization separation circuit 4 is 20H (2
20 to detect 83H) and 40H (303H), respectively.
H detection circuit 7, 40H detection circuit 8, and scanning line counter 9
supplied to

The output iri when the 20H detection circuit I detects 20H (283H) is supplied to the 20H extraction circuit 6, and the 20H of the video signal obtained by shaping the video signal with the waveform shaping circuit 3.
The signal superimposed on the eyes, that is, the character signal, is extracted there.

When displaying a character signal on a television screen, it is up to you which horizontal scanning line to use as the first line, but in this example it is U40H, so the 40H detection circuit 8 selects the 40H line.
H (303H) is detected and the output is sent to the scanning line counter 9.
to be introduced.

This scanning line counter 9 receives an H pulse,
This is counted, and the 40H (283H) is IH in relation to the output of the fl40H detection circuit 8.
The count starts as 208, and stops when the count reaches 208.

The output of the 20H sampling circuit 6 is transferred to a buffer memory 10, a program comparison circuit 11, a scanning line comparison circuit 12, and an STX detection circuit 13.
supplied to

A signal from the program selection switch 15 is input to the program code comparison circuit 11, and the program code of the sent superimposed signal, that is, the program code from the 20H extraction circuit 6 and the signal selected from the program selection switch 15 is inputted to the program code comparison circuit 11. Compare the signals of the programs being played and obtain an output signal when they match.

Note that the program selection switch 15 can select 10 different programs.

The scanning line comparison circuit 12 compares the scanning line code sent from the 20H sampling circuit 6 with the output of the scanning line counter 9, and when the two match, outputs an output signal.

The STX detection circuit 13 detects the STX of the superimposed signal, that is, the STX sent from the 20H extraction circuit 6, and controls the timing of the clock of the clock generation circuit 14.

The color subcarrier reproducing circuit 5 extracts the color burst signal for each LH and reproduces the fsc color subcarrier.

This signal is input to the clock generation circuit 14, and therefore, fsc(5,7 3 MHz) and fsc(
A clock of 2.86 MHz) is generated in accordance with the output from the clock generation circuit 14 under the synchronized timing of the STX.

1.fsc is used for reading character signal portions into and from the buffer 10 and main memory 7.

Also, the fsc is used to read out program codes and scanning line codes to and from the program comparison circuit 11 and the scanning line comparison circuit 12.

The outputs of the program comparison circuit 11, the scanning line comparison circuit 12, and the clock generation circuit 14 are supplied to the control circuit 20, which generates gate signals and gate signals necessary for the buffer memory 10, rewrite gate 16, and main memory 1 based on appropriate timing. Send a clock signal.

That is, when the programs match, the character signal portion is read into the buffer memory 10 by the control circuit 20 in accordance with the output signal from the program comparison circuit 11.

Note that this is performed in a 20H (283H) period.

The signal read into the buffer in this way is
When the scanning lines match, the control circuit 20 opens the rewrite gate 16 in response to the output signal of the scanning line comparison circuit 12 and transfers the IH character signal portion from the buffer memory 0 to the main memory 1. is stored and memorized.

This main memory stores 17 characters of character signals for 1 screen (8 lines), and its capacity is 245 x 208 x 25.
0960 bits are required, and the stored contents go through one round in the ■ field.

Here, according to the signal from the scanning line counter 9, 40H (
For each H from 283H to 248 (491H), 245 bits, which are the character signal portion for IH corresponding to the H, are read out from the main memory 17 by the control circuit 20, for example, a 245-bit generation circuit included therein, and rewritten. gate 1
6 to the main memory 17 and thus the main memory 11
The contents of the field are repeated twice for each field.

As mentioned above, when the rewriting gate 16 is opened to pass a signal from the backup memory 10, the signal is stored in the main memory 17, that is, rewriting is executed. The state is sent to the main memory 17.

When the stop button 21 is pressed, the contents of the main memory 17 are not rewritten, and the current character signal portion is stored as is.

That is, in the rewriting gate 16, the input from the buffer memory 10 is closed, while only the circulation signal from the main memory 11 passes through.

The mixing circuit 181d passes the signal from the main memory 11 as it is when displaying only the character signal portion and displays it on the display 19, and when displaying the character signal portion by superpausing the normal TV image, the main The signal from the memory 17 and the video signal are mixed and displayed on the display 19.

The above is an overview of the teletext receiving apparatus, but when the transmitted television signals are out of synchronization, the following phenomenon occurs.

On the transmitting side, synchronization signals may become out of synchronization, for example, when switching from a camera to a VTR or between a central station and a local station.

Such an example is shown in FIG. 4, for example.

Suppose that the signal F1 is switched between, for example, 100H and IOIHO.

Here, although the signals F and I/i are not actually transmitted after switching, they are written to make the synchronization relationship easier to understand in the later explanation.

Signal F2 shows the signal after switching, and 16 of signal F2
Switching occurs at 0H.

Signal F is a signal that is actually transmitted.

The scanning line counter 9 counts up from 40Ht-"1" and stops counting at "208", that is, 247H.

As shown in FIG. 4, when switching occurs within 100H, a signal of 161H after switching comes next.

Therefore, the scanning line counter 9 continues counting with this 161H as the 62nd H pulse, but if the vertical synchronization signal comes before counting up to 208H, it will be reset here, so it will stop counting before reaching 208H. I end up.

The output of the scanning line counter 9 is usually an H pulse from 40H to 247H that is introduced into the control circuit 201.

The character information that is the content of the main memory 11 is from 40H to 247.
245 bits are shifted per IH between H, and therefore one cycle is completed with a shift of 2 4 5 × 208:50960 bits in 208H.

Here, the 245 clock generation circuit in the control circuit 20 receives H pulses from OH to 245H only from the scanning line counter 9 and outputs a 245-bit clock to the main memory 17 for each IH.

If only fewer H pulses than 208H come to the control circuit 20, it will not be possible to obtain enough clocks to send the character information to the main memory 17 once, so when the output of the main memory 11 is displayed, the lines will be shifted and normal. It will no longer look like a character.

In addition, the 245 pit generation circuit uses ■pulse (H synchronization signal)
For example, 1 6 1 H (
7) When the H pulse comes in the middle of sending out the 245-bit clock from the 245-bit generation circuit, the 245-bit
Since the 245-bit generation circuit is reset before becoming a bit, the amount of UIH sent (245 bits) is not sent to the main memory 17, and the IH shift amount becomes less than 245 bits, resulting in distorted displayed characters.

Furthermore, when the switching period extends over several H or several V, there is no H pulse during that period, so if a dynamic shift register is used in the main memory 17, character information may disappear.

As described above, if a synchronization difference occurs in the transmitted television signal, characters will be distorted during projection.

It is an object of the present invention to provide a teletext receiving device that prevents the above-mentioned synchronization deviations of television signals from having an adverse effect on the display. The reading of character information from the main memory is made to complete one cycle without interruption, and one embodiment thereof will be described below.

FIG. 5 shows a block diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 3 are designated by the same reference numerals.

In this embodiment, a synchronization correction circuit 300 is provided after the synchronization separation circuit 4.
It is characterized by the additional provision of.

This synchronization correction circuit 300 inputs the synchronization signal from the synchronization separation circuit 4 and the color subcarrier fsc from the color subcarrier regeneration circuit 5, and supplies the output to the 20H detection circuit 1 and the 40H detection circuit 8. The output is supplied to the scanning line counter 9, and another output is introduced to the 245 clock generation circuit (245 bit generation circuit) of the control circuit 20.

This synchronization correction circuit 300 is configured such that when a phase shift of the synchronization signal occurs due to switching of the television signal, the reading of character information from the main memory is carried out twice, for example, so that the reading of character information from the main memory is repeated twice, that is, the reading of l fields is read out so as not to cause display disturbance. A corrected vertical synchronization signal is obtained that is corrected to ignore the vertical synchronization signal if it is introduced before completion, and a horizontal synchronization signal is introduced before the reading of one scanning line of character information from the main memory is completed. This is ignored and a corrected vertical synchronization signal is obtained which is corrected to occur after the completion of the process, and the latter is used as the input of the scanning line counter 9 and as the reset input of the 245-decimal counter of the 245 clock generation circuit. On the other hand, the former is used as a reset input for the scanning line counter 9.

FIG. 6 shows a block diagram illustrating the configuration of the synchronization correction circuit 300 in detail.

Here, 301 to 303 are monostable multivibrators triggered by the falling edge of the input pulse, and 304 to 30
5 is a monostable multiviprator triggered by the rising edge of the input pulse.

301 is a flip flop, 308 and 309F
i delay circuit, 310 to 314 and 318 are OR gates, 316 and 317 are AND gates, 319 is a NAND gate, and 4 is a vertical synchronization signal separation circuit.

Note that 304 and 315 are inverters.

The operation of the synchronization correction circuit 300 will be explained with reference to the timing chart of FIG.

The time required for switching from a camera to a VTR, etc. on the broadcasting side is not constant, and various cases can be considered, although it is usually short within one vertical period, but an undisturbed display can be performed as shown below. Ru.

The synchronization signal SA output from the synchronization separation circuit 4 is introduced into the 20H detection circuit 7 and the 40H detection circuit 8, and is input into the monostable multivibrator 301.

This monostable multivibrator 1 is triggered by the falling edge of the pulse of the synchronization signal SA, and is activated during one horizontal period (63.5μ
It generates a pulse with a width of about 60 μs, which is slightly shorter than s).

A synchronizing signal SA is introduced into a flip-flop 307 which receives the output SB of the monostable multiviprator 301 as a reset signal.

This monostable multivibrator 30Hj:, synchronization signal S
If there is a pulse within 60μs of the previous pulse of A, the output SB will remain high to be retriggered, and if there is a pulse after 60μs then the output SB will remain high for 60μs.
Afterwards, the output SB becomes a low level and rises to a high level in response to the next pulse.

That is, the output SB of the monostable multiviprator 301 is
The high level continues when there is a next pulse that falls less than 60 μs from the fall of the previous pulse of the synchronization signal SA, so that the next pulse falls 60 μs or less from the previous pulse.
In other words, it is determined that the horizontal synchronizing signal is earlier than in the normal case without the switching, that is, that the switching has occurred, and that it is a synchronizing signal period with an equalization pulse.

When the output SB of the monostable multi-bicycle brake 301 is at a high level, the output Sc of the flip-flop 301 is inverted from high level to low level in response to the fall of the synchronizing signal SA pulse, if any, and is inverted for the above 60 μs. It becomes high level during the next pulse from the horizontal synchronization signal that occurred within a period of time, and becomes high level every pulse during the synchronization signal period with the equalization pulse.

The synchronization signal SA is delayed by several nanoseconds in the delay circuit 309, and is used as the synchronization signal SA.

Note that this synchronization signal SA has an extremely short delay time, so
In FIG. 7, it is shown without distinguishing it from the synchronization signal SA.

The synchronizing signal SA and the signal Sc are passed through an OR gate 310 to obtain a signal SD.

Here, the synchronization signal is also
Since the signal Sc triggers the synchronization signal SA, when the leading edge of the rising signal Sc lags behind the falling edge of the synchronization signal SA, an extremely thin low-level pulse is generated in the signal SD. Therefore, in order to prevent this, a synchronization signal SA that is delayed from the synchronization signal SA is used.

This signal SD is obtained as a horizontal synchronization signal from which only the horizontal synchronization signal within 60 μs from the previous horizontal synchronization signal in the synchronization signal SA has been removed, and a signal whose level fluctuates high and low during the vertical synchronization signal period.

This signal SD is the signal S delayed by 2 μs in the delay circuit 308.

and is further input to the monostable multivibrator 302.

This monostable multiviprator 302 is triggered by the falling edge of the signal SD to obtain a pulse with a width of 58 μs, and the signal SD
Output.

This signal S″D is obtained by the delay circuit 308 as a pulse with a rise width of 58 μs with a delay of 2 μs from the fall of the signal SD.

Therefore, the signal S//D is at least at a low level in the portion corresponding to the horizontal synchronizing signal of the signal SD, and moreover, the signal S//D is at a low level by 2 μm from the falling edge of the vertical synchronizing signal period of the signal SD.
It is at a low level during s.

An OR gate 31 receives the signals SD and SI/D.
A signal SD is obtained as the output of 1.

This signal SD is the signal S.

It is obtained as a signal that is at a low level for 2 μs from the fall of the horizontal synchronizing signal portion of the signal SD and the vertical synchronizing signal portion of the signal SD.

That is, the signal SD consists of a horizontal synchronization signal group in which only the horizontal synchronization signal that comes within 60 μs from the previous horizontal synchronization signal is removed, and a signal group in the vertical synchronization signal part that has the same intervals and pulses as a normal horizontal synchronization signal. .

In other words, the signal SD consists of pulses having the same interval and width as a normal horizontal synchronizing signal, with only the horizontal synchronizing signal coming within 60 μs from the previous horizontal synchronizing signal being removed by the above switching.

Since the monostable multi-bi break 302 is at a high level during the character display period, it serves to eliminate the horizontal synchronization signal that arrives during the character display period, and the signal SD is a horizontal It becomes a synchronization signal.

This signal S.

The monostable multivibrator 303 to which is input is capable of outputting a pulse that is triggered at the falling edge of the signal SD and remains at a low level for 65 μs, thereby obtaining a signal SE.

This signal SE maintains a low level in order to retrigger the monostable multiviprator 303 if the pulse interval of the signal SD is within 65 μs, which is longer than the normal horizontal synchronization signal interval, but if it is longer than 65 μs, The monostable multivibrator 30 becomes high level and the next pulse
Maintain high level until 3 is triggered.

Therefore, the signal SF is at a high level because the pulse interval between the previous and next pulses of the signal SD is 65 μs or more.In other words, due to the above switching etc., the phase between the horizontal synchronizing signals is shifted from normal This occurs when the time is within 60 μs or 1d65 μs or more.

Here, the monostable multivibrator 303
The period is not limited to , but may be any suitable length longer than one horizontal period.

Monostable multivibrator 3 to which this signal SE is input
04 becomes high level when triggered by the rising edge of the signal S)i, and generates a pulse with a width of 18 mS as the output signal SG.

OR gate 312 which receives this signal SG and signal S0 as input
A signal ST is obtained as an output.

This signal ST has a high level period of 18
When it is less than ms, it is Fl 1 8 ms, and when it is more than 18 ms, it is at a high level during that time.

This signal STH is input directly to AND gate 316 and then to AND gate 317 through inverter 315 .

The other input terminal of the AND gate 316 receives a pseudo horizontal synchronization signal obtained by dividing the output of the color subcarrier recovery circuit 5 by 2/455 in the frequency dividing circuit 320, and the AND gate 316 receives the signal ST is open during the high level period to pass this pseudo horizontal synchronization signal, which is the OR gate 31.
8 and an AND gate 319 to output it as a signal SH.

In addition, the signal SD is inputted to the other input terminal of the AND gate 311 through the inverter 304, and the AND gate 311
317 is open while the signal ST is at a low level and passes a signal obtained by inverting the signal SD, that is, a horizontal synchronization signal, which is outputted as a signal SH through an OR gate 318 and an AND gate 319.

In this way, when the signal SR becomes high level, that is, when the next horizontal synchronization signal is sent from the transmitting side within 60 μs or 65 μs after the previous horizontal synchronization signal due to the above switching, etc., the color sub A pseudo horizontal synchronization signal obtained by frequency-dividing the carrier signal is output as a signal SH.

In other words, if the above switching is made on the transmitting side, if the interval between horizontal synchronization signals sent is within 60 μs or 65 μs or more, this will be detected and a pseudo horizontal synchronization signal will be output as signal SH, and if the interval between horizontal synchronization signals sent is within 60 μs or 65 μs or more, this will be detected and a pseudo horizontal synchronization signal will be output as signal SH; For less than 65 μs, the signal SD is output as the signal SH.

Of course, if the above switching is not performed, the signal SD is output as the signal SH.

This signal SH is equivalent to the horizontal synchronizing signal and is introduced as an input to the scanning line counter 9, and also as a reset signal for the 245-base counter of the 245 clock generating circuit.

This scanning line counter 9 receives 40H from the 40H detection circuit 8.
In response to the output when the signal SH is detected, counting is started using the pulses of the signal SH as a horizontal synchronizing signal.

Then, the 245-decimal counter of the 245 clock generation circuit is reset using the pulse of the signal SH as a horizontal synchronization signal and starts counting the 5.73 MHz clock from the clock generation circuit 14, and from this reset until it counts 245, 5 from the clock generation circuit 14. 7
The configuration is such that a 3 MHz clock is supplied from a 245 clock generation circuit.

In addition, the 245 clock generation circuit uses this 5.73MHz
By supplying the clock in response to the output when the scanning line counter 9 detects 40H to 247H, the clock of 245 is generated only during the display period of 40H to 247H, and this is supplied to the main memory 17. and display is executed.

Here, signal SH and scanning line counter 9 40H to 24
40H to 247 in response to the output when 7H is detected.
If the 245-decimal counter is reset during the 245 clock generation circuit, the 5. 7 3MHz
It is not necessary to control the supply as described above.

The signal SH is used as a horizontal synchronizing signal, but since pulses are obtained at intervals of 60 μs or more as described above, a heliset signal is introduced while the 245 counter is counting up to 245. Therefore, reading of character information from the main memory 110 is not interrupted in the middle of each scanning line.

Then, the vertical synchronizing signal sent during the character display period of one field is ignored due to the above-mentioned switching or the like in the following manner.

The vertical synchronization signal SP is separated from the synchronization signal SA, which is the output of the synchronization separation circuit 4, by the vertical synchronization separation circuit 4.

This vertical synchronization signal SP is applied to the monostable multivibrator 30.
5, where it is output as a signal SQ with a pulse width of 16 mS that is triggered at the rising edge and becomes high level.

The signal SP obtained by the OR gate 313 inputting the signals SQ and SP is the same as the signal ST and the OR gate 314.
A signal Sv is obtained as its output.

This signal Sv is inputted as a reset signal for the scanning line counter 9.

When the signal SD becomes a pulse interval of 65 μs or more and the signal ST becomes a high level for 18 mS or more as described above, the signal Sv also becomes a high level during this period, which becomes a vertical synchronization signal period, and the signal SR becomes a low level. Even if something happens, it will be ignored and the scanning line counter 9 will not be reset.

In addition, the signal SD has a pulse interval of 60 μs to 65 μs as described above.
If the time is less than μs and the signal ST becomes low level,
The vertical synchronization signal as mentioned above cannot be ignored, but in response to the previous vertical synchronization signal, the signal SQ is 167? Since it is at a high level during the period Zs, if a vertical synchronization signal is sent during this period, it will be ignored.

The vertical synchronization signal sent after the end of such an ignored period passes through OR gates 313 and 314 and becomes a low level signal Sv, which is input to the scanning line counter 9 as a vertical synchronization signal and reset.

In this way, the scanning line counter 9 is not set to UIJ within 1677ZS from the rise of the vertical synchronizing signal, that is, it is not reset during the character display period, so that the 17 fields of character information in the main memory 17 Reading will not be interrupted in the middle of the process.

The operation of the synchronization correction circuit 300 is shown in the timing diagram shown in FIG.

In this figure, the switching period in the above switching is indicated by diagonal lines.

FIG. 71 corresponds to the case where the above switching is not performed, and the synchronization signal AK response that is sent? signal SD,
As a result, pulses with an interval of 1 water half period are obtained as SH,
It is used as a horizontal synchronization signal, and a vertical synchronization signal is outputted as the signal SP and thus S.

FIG. 72 corresponds to the case where the switching period is one horizontal period or less, the switching is during a character display period, and the horizontal synchronizing signal after switching is within 60 μs from that before switching.

In this case, since the first horizontal synchronization signal after switching is ignored, the pulse interval of the signal SD increases, so the signal SE
becomes high level, and signal ST also becomes high level.

As a result, the clonk or pseudo horizontal synchronization signal from the divider 320 is output as the horizontal synchronization signal to signal sH.

When the first horizontal synchronization signal after switching comes within 18 mS from the rise of the signal S00 to high level, since the signal ST is high level, a pseudo horizontal synchronization signal is output as the signal SH, and the vertical synchronization signal comes and the signal Even if SP becomes a low level, it is ignored and is not output to the signal Sv, and this 1877Z
After S has elapsed, the signal SD is output as the signal SH.

Also, if the first horizontal synchronizing signal after switching comes 18 ms after the high rise of signal S8, the signal S
.

Furthermore, since ST is at a high level, signal SD is not received until after ST has arrived. It will be output as the number SH.

3 corresponds to the case where the switching period is one horizontal period or less, the switching is in the character display period, and the horizontal synchronizing signal after switching is 60 ms or more and less than 65 ms from that before switching. .

to the periodic signal sA. The signal SD obtained in response is output as the signal SH because its pulse interval is not 65 μs. On the other hand, the signal S is at a high level for 16 ms from the rise of the vertical synchronization signal immediately before switching, so the signal SD is output after switching during this period. Even if the first vertical synchronizing signal arrives and the signal SP becomes low level, this is ignored and the signal Sv does not go low level.

FIG. 7 41ri, the switching period is one horizontal period or less,
This corresponds to the case where the switching occurs during the equalization pulse before the vertical synchronization signal.

At this time, if the first pulse of the signal SD after switching is 60 μs or more and less than 65 μs from the pulse before switching, the signal SD is output as the signal SH. 1. More than 6 ms has passed and the signal SQ is at a low level.
Since P remains at a high level until the next vertical synchronization signal arrives, the vertical synchronization signal is output as the signal SP, and thus the signal Sv, only after the next vertical synchronization signal arrives.

Note that the reason why the first vertical synchronization signal after switching is not ignored is that the switching occurs within 16 minutes from the rise of the vertical synchronization signal before switching.
This is because there is no problem even if the vertical synchronization signal is output after ms has elapsed and the display period has ended.

FIG. 15 corresponds to the case where the switching period is less than one horizontal period and the switching is during the equalization pulse period after the vertical synchronization signal.

If the first pulse of the signal SD after switching is 60 μs or more and less than 65 μs from the pulse before switching, the signal SD
On the other hand, since the signal SQ is at a high level for 16772S from the rise of the vertical synchronization signal immediately before switching, even if the signal SP becomes low level due to the vertical synchronization signal sent during this period, is this possible? is ignored and the signal S
It will not be output to v.

FIG. 7 corresponds to the case where the switching period is within one field and the switching is a display period.

At this time, the signal SD has a pulse interval of 65 μs due to switching.
The signal ST becomes high level for 18 ms from the time it exceeds this point and is output as a pseudo horizontal synchronization signal S, while even if a vertical synchronization signal arrives during that time, it is ignored and does not appear in the signal Sv. do not have.

In FIG. 7, the switching period is within one field, and the switching corresponds to 8 phases in the equalization pulse period, and from the time when the pulse interval of the signal SD exceeds 65 μs due to switching, 1 8 During the period 77ZS, the pseudo horizontal synchronization signal is output as the signal SH, while even if a vertical synchronization signal arrives during that period, it is ignored and does not appear in the signal Sv.

FIG. 7 and 8 correspond to the case where the switching period exceeds one field and extends over several fields, and during the switching period, the signal E and thus the signal T are supplied as the pseudo horizontal synchronizing signal SH while the signal T continues to be at a high level. On the other hand, even if a vertical synchronizing signal arrives, it is ignored and does not appear in the signal Sv.

As described above, when there is switching from a camera to a VTR, etc. on the transmitting side, when the switching is detected by the sent synchronization signal, especially the horizontal synchronization signal, that is, the monostable multivibrator 303 is activated. When the output becomes a low level, a pseudo horizontal synchronization signal is obtained as a horizontal synchronization signal in the signal SV, so that the interval is not too small, and during that low level, the vertical synchronization signal is ignored and the signal Sv , so the interval between them cannot be too small.

In addition, when there is a switching as described above, if the switching is not detected, that is, if the synchronization signal after switching is sent at a timing when the monostable multivibrator 303 does not operate, the synchronization signal after switching is transmitted. The horizontal synchronizing signal is obtained as an output on the signal SH, so that the interval is not too small, and even if the vertical synchronizing signal arrives within a certain period of time, that is, the display period of one field, from the vertical synchronizing signal immediately before switching, it is ignored and the signal Sv Therefore, the interval between the signals Sv will not be too small.

In this way, when the above switching occurs, the signal SH becomes 1
The signal Sv is not output as a horizontal synchronizing signal within the display period of a scanning line, and the signal Sv is not output as a vertical synchronizing signal within the display period of the 1 field.

Note that the color subcarrier regeneration circuit 5 freely oscillates at the frequency fsc and is synchronized with the color burst signal S6, and even if the color burst signal stops coming due to the above switching etc., the free oscillation continues, so The output signal is not interrupted, and the pseudo horizontal synchronization signal is generated.

By the way, the main memory 17 requires 50960 bits,
In reality, memory with such a value cannot be obtained, for example, 102.
If you decide to use 4X50 two 51200 bits, it will be 240
This results in an extra bit.

Therefore, when going through character information in one field, 24
It is necessary to provide an extra 0 bit of clock to main memory.

If a dynamic shift register is used as the main memory 17, it is also necessary to provide the main memory with a clock for refreshing.

A control circuit 20 that satisfies both of these needs.
An embodiment of the reading section will be described with reference to FIG.

Normally, this extra clock (sending clock) is output when the character information display period (40H to 247H) ends, that is, between 248H and 40H of the next field.

2 from the clock generation circuit 14; The 8 6 MHz clock is converted to 1 4 3 KHz by the frequency divider 21 and then to I KHz by the frequency divider 22.

This I KHz clock is introduced into one input terminal of AND gate 23, and passes as its output during the period when the signal SK introduced into the other input terminal of AND gate 23 is at a high level.

This signal SK becomes a high level output when the scanning line counter 9 finishes counting 208 and begins 209, that is, when 248H is detected, and is reset to a low level at the fall of the signal Sv.

Also, the 143 KHz clock which is the output of the frequency divider 21 is introduced into one input terminal of the AND gate 24, and its signal SL, which is introduced into the other input terminal of the AND gate 23, is at a high level. Pass as output.

This signal SL is set to a high level at the fall of the signal Sv, and becomes a low level at the output when the scanning line counter 9 detects 40H.

25 is or gate, 26 is and gate, 27 pa240
The 240-decimal counter 27 is a display period of 40H to 247H, for example, the scanning line counter 9 is 40H.
When 248H is detected, that is, from "1" to "209", an appropriate signal is introduced and reset, a high level is input to the AND gate 26, it is opened, and after 240 counts, a low level is input to the AND gate 26. and close it.

Here, the output of the AND gate 26 and the output of the 245 clock generation circuit are introduced to the main memory 17 etc. through the OR gate 28 as a read and send clock.

FIG. 9 shows a timing diagram illustrating the operation of the read portion of the control circuit.

After the display period ends, the signal SK becomes high level and IKH
The clock of z is introduced through an AND gate 26 into a 240-decimal counter and counted therein, while the clock of signal S
M is introduced as a sending clock to the main memory 17 side, and when the signal Sv falls due to the arrival of the vertical synchronization signal, a 143 KHz clock is introduced to the 240-decimal counter through the AND gate 26 and counted there, while the signal SM It is introduced into the main memory 17 side as a clock and serves as a sending clock.

Eventually, when the 240-decimal counter 21 reaches 240, the AND gate 26 is closed, and the sending clock 2
The supply of 40 ends.

Then, so that the count to 240 of the 240-decimal counter 2T is completed before 40H,
A frequency of 4 3 KHz is selected, and IKHz, which is necessary for refreshing the main memory 17, is selected.

At this 40H, the signal SL becomes low level and 1
The supply of 43 KHz to the AND gate 26 is also stopped.

Here, the 245 clock generation circuit, which receives the 5.73 MHZ signal from the signal S which is at a high level from 40H to 248H of the signal SH, is reset as described above by the signal SH until it counts 245. 5.
By introducing 73MHz to ORGATE 28, 40MHz
From H to 248H, 245 clocks are introduced into the main memory 17 for each pulse (horizontal synchronization signal, pseudo-horizontal synchronization signal) of each signal SH, and read character information from the main memory 17, and eventually display it. Helpful.

Now, suppose that the signal S1 is switched to the signal S2 on the transmitting side as shown in FIG.
A clock from 0H to 5.73MHz is used for each horizontal scanning period 2.
45 signals SN are obtained as the output of the OR gate 28.

After switching, when the signal SG becomes high level, it changes to 248H according to the pseudo horizontal synchronization signal, and when it is low level, it changes to 248H according to the signal SD.
5. A 73 MHz clock is obtained as the output of the OR gate 28 as the 245 signal SN for each horizontal scan period.

Thereafter, the IKHz clock is used as the signal SM until the fall of the vertical synchronization signal output as the signal Sv after switching the signal S2.
Thereafter, the 143 KHz clock is outputted as the signal SM until the clock reaches 40H, and the total of 240 clocks including the IKHz clock.

In this way, if the capacity of the main memory 17 is greater than the capacity of the text information, the text information is properly read out and, in turn, displayed.

Note that if the main memory 17 has extra capacity, even if there is some fluctuation in the operation of the circuit, the influence of it will be reduced.
The display can be stabilized.

Incidentally, it is of course possible to store and read out character information by applying known means, and is not limited to the above embodiment. A RAM is used as a so-called main memory, and this writing and reading is performed using a vertical synchronization signal and a horizontal synchronization signal. Modifications such as those that can be realized by appropriately specifying addresses in relation to signals etc. are also possible.

According to the teletext receiving device of the present invention, as described above, even if a synchronization difference occurs in the television signal due to switching from a camera to a VTR, etc. on the transmitting side, the synchronization correction circuit will synchronize the TV signal by this switching. Horizontal synchronization signal after switching due to misalignment,
Even if the vertical synchronization signal is sent earlier than the normal interval, the signal is corrected to an interval that is around the normal interval and does not interfere with the display of character information, and is used as a horizontal synchronization signal.
Since it is possible to output a signal as a vertical synchronization signal, it is possible to prevent the adverse effects of synchronization deviation due to switching, and it is useful for properly displaying characters and the like.

[Brief explanation of the drawing]

FIG. 1 is a drawing explaining a character signal, FIG. 2 is a state diagram explaining the structure of a character signal displayed on a television screen, and FIG. 3 is a block diagram of a character signal receiving device.
FIG. 4 shows a state diagram when switching occurs on the transmission side of television signals, FIG. 5 shows a block diagram of an embodiment of the teletext receiving device of the present invention, and FIG. 6 shows the same synchronization as described above. FIG. 7 is a block diagram of the correction circuit, FIG. 7 is a timing diagram explaining the above operation, FIG. 8 is a block diagram of the clock generator, and FIG. 9 is a timing diagram explaining the operation. are shown respectively. 4: Synchronization separation circuit, 5: Color subcarrier regeneration circuit, 7:20
H detection circuit, 8: 40H detection circuit, 9: Scanning line counter, 14: Clock generation circuit, 17: Main memory, 20: Control circuit, 300: Synchronization correction circuit, 301 to 305: Monostable multivibrator, 307: Flip - Flop, 308 and 309: delay circuit, 320: frequency divider.

Claims (1)

[Claims] 1. Receive character signals such as characters, figures, etc. multiplexed during the vertical retrace period of a television signal, accumulate and store this character signal in the main memory using clock pulses synchronous with this,
In a teletext receiving device configured to display a continuation of the broadcast, means for dividing the frequency of a color subcarrier signal obtained from a color subcarrier reproducing circuit to create a pseudo horizontal synchronization signal;
means for detecting synchronization deviation by determining whether or not the intervals of horizontal synchronization signals sequentially obtained from the synchronization separation circuit are regular intervals; and horizontal synchronization at that time when a synchronization deviation is detected by the detection stage K. means for outputting the pseudo horizontal synchronization signal instead of the previous horizontal synchronization signal after a predetermined interval has elapsed since the previous horizontal synchronization signal; It is equipped with a synchronization correction circuit consisting of a means for outputting a signal as a vertical synchronization signal appropriately after a predetermined interval has elapsed since the previous vertical synchronization signal, and compensates for synchronization deviation due to switching on the transmission side of the television signal. A teletext receiving device characterized by obtaining a horizontal synchronization signal and a vertical synchronization signal.