JPS587065B2 - Semiconductor device with high resistance layer and method for manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming a high resistance layer in silicon.

Forming a high resistance layer in silicon with good controllability is an essential technology for manufacturing semiconductor integrated circuits.

When a normal diffusion layer is used, a layer resistance of only several hundred ohms/square can be obtained, so if a high resistance value is to be achieved, it is necessary to lengthen the resistor, which causes a reduction in the degree of integration.

Even higher layer resistances can be obtained by double diffusion, but their controllability is poor.

On the other hand, when using an ion-implanted layer, a high-resistance layer can be formed relatively easily by using a low implantation amount.

Conventionally, P-type impurities, particularly boron, have been used to form high-resistance layers.

The reason for this is that the mobility is low, and when an NPN bipolar transistor is included, the layer formed along with the base formation can be used as a high resistance layer.

Attempts to form a high resistance layer using boron ion implantation include the use of radiation damage by additional implantation of inert ions in addition to single implantation.

On the other hand, there have been very few attempts to form a high resistance layer using N-type impurities.

The reason for this is that it has high mobility, and if an NP-type bipolar transistor is included, the layer formed along with emitter formation must be used as a high-resistance layer.
This is contrary to the requirement for low resistance for the emitter layer.

In this case, one method is to use the radiation damage described above.

However, high resistance layers based on mere radiation damage (P type,
Both N-type devices have the following drawbacks: (a) resistance decreases through a heat treatment process; and (b) resistance decreases due to temperature rise during operation of the element.

Therefore, if a method capable of avoiding (a) and (b) is developed, it will be possible to use the N-type emitter forming layer as a high-resistance layer.

The present invention has been made in view of the above circumstances, and is characterized by utilizing a phenomenon unique to the combination of arsenic atoms and neon atoms in silicon, and its purpose is to form an N-type high resistance layer in silicon. It is in.

In the present invention, neon ions are implanted into the entire surface or part of an arsenic-doped layer formed in advance in silicon, and then heat-treated at high temperatures.The layer resistance of the sample is compared to that of the original arsenic-doped silicon. It is based on a phenomenon unique to the combination of arsenic and neon atoms in silicon, which causes them to grow abnormally large.

That is, an N layer of arsenic is formed on a P-type silicon substrate, and this N layer is
This phenomenon is characterized by the use of layers, and this phenomenon does not occur with P layers (boron-doped layers) (if neon is implanted into a boron-doped layer and subjected to high-temperature heat treatment, the resistance becomes low).

) Therefore, this is a phenomenon unique to arsenic and neon within this range.

Next, we will discuss the details of this phenomenon.

Arsenic is introduced into a P-type silicon substrate with a specific resistance of about 10 Ωcm to form an N layer by thermal diffusion, or arsenic is introduced by ion implantation and heat treated at high temperature to form an N layer (sample A).

Let ρA be the layer resistance of the N layer separated by the PN junction.

Next, neon ions are implanted by selecting acceleration energy so as to approximately match the arsenic concentration distribution in sample A.

If the layer resistance of Sample B, which was then heat-treated at a high temperature, is ρS, then the relationship ρA<ρB is always found.

In this case, even for sample A0, which has only introduced arsenic by ion implantation (i.e., the implanted layer has not been activated by high-temperature heat treatment), instead of sample A, after the same treatment, ρA<ρB The following relationship is found (here, ρ
A is the layer resistance when sample A0 is heat-treated at a high temperature to become sample A).

This fact indicates that the above phenomenon does not essentially depend on the amount of defects introduced by ion implantation.

Numerical examples based on the latter process are shown in the table.

From this, it can be seen that under the same conditions of the same substrate, implantation energy, heat treatment time and heat treatment temperature after neon ion implantation, the larger the amount of neon ions implanted, the larger ρB/ρA becomes.

As a result of studies such as carrier distribution measurements, it has been found that the above phenomenon is due to the fact that the carrier concentration is greatly reduced due to the formation of a complex between arsenic atoms and neon atoms at arsenic concentrations of 1018 CrrL-3 or higher.

The above-mentioned arsenic concentration of 10<18>cm<-3> or more is the result of carrier concentration distribution measurement.

That is, arsenic, for example, at 220 KeV, I X 1 0 l4
The carrier distribution of the sample subjected to cm-2 injection and heat treatment at 900° C. is as shown by the broken line in FIG.

Also, after implanting arsenic under the same conditions, neon was implanted at 150 KeV, 2×1
The carrier distribution of the sample injected at 510-2 cm and heat-treated at 900° C. is as shown by the solid line in FIG.

From Figure 3, the distribution below 1018CmIrL-3 is almost the same for arsenic only and for arsenic + neon, but the distribution for arsenic only and above 1018σ-3 can be changed to 1018cIrL-3 by injecting neon. is decreasing.

Therefore, it can be said that this is a phenomenon related to arsenic of ~1018cTL-3 or higher.

Therefore, by utilizing the above phenomenon, the steps shown in the figure can be performed.

Next, an example will be described with reference to the figures.

FIGS. 1a, b, and c show a method for selectively forming a high resistance layer within a low resistance layer.

That is, as shown in FIG. 1a, when arsenic is introduced into the P-type silicon wafer 2 by thermal diffusion or ion implantation to form an arsenic doped layer 1, as shown in FIG. A region other than the region to be made resistive is covered with a mask 3 made of silicon dioxide or the like, and neon ions 4 are implanted.

Next, as shown in FIG. 1C, the high resistance layer 5 can be selectively formed within the low resistance layer 6 by heat-treating this at a high temperature.

FIGS. 2a and 2b show a specific application of the process shown in FIG. 1 a+b+c, and show an example of manufacturing a high-resistance element using an emitter forming layer.

That is, as shown in FIG. 2a, at the same time as forming the emitter of the NPN bipolar transistor, a highly arsenic doped layer 1' is formed on the P-type silicon wafer 2' using silicon dioxide 7 or the like as a mask.

Next, as shown in FIG. 2b, a high resistance layer 5' is formed in the low resistance layer 6' by the same process as in FIG. By installing the electrode 8, a high resistance element with good ohmic contact can be manufactured.

As explained above, the present invention differs from methods that simply use radiation damage, and utilizes the above-mentioned properties specific to arsenic atoms and neon atoms in silicon. There is an advantage that a high resistance layer that is stable even when the device is in operation and also stable against temperature increases during operation of the device can be manufactured from a low resistance layer that has already been formed.

In addition, as shown in Figure 2, the already formed low resistance layer (
selectively implanting neon ions into the N+ emitter formation layer,
When a high-resistance layer (N single layer) is formed by high-temperature heat treatment, there is an advantage that an extra step (forming an N+ layer) for making ohmic contact with an electrode is unnecessary.

[Brief explanation of the drawing]

Figures 1a, b, and c are schematic cross-sectional views showing the formations in each step of an embodiment of the present invention, and Figures 2a and b are specific examples of the formations in each step of the embodiment of the present invention. A cross-sectional view showing
FIG. 3 is a depth-carrier concentration characteristic curve showing an example of carrier concentration distribution measurement results according to the present invention. 1... Arsenic doped layer, 2... P-type silicon wafer, 3... Mask, 4...
Neon ion, 5... High resistance layer, 6...
・Low resistance layer, 7...Silicon dioxide, 8...
···electrode.

Claims (1)

[Scope of Claims] 1. A semiconductor device having a high-resistance layer in which a region in which an element different from an element constituting the semiconductor substrate is introduced is provided in a part of a semiconductor substrate, and the region is used as a high-resistance layer. 1. A semiconductor device having a high resistance layer, wherein the resistance layer region is configured by introducing an arsenic element, and a neon element is introduced into a part or all of the area into which the arsenic element is introduced. 2. A step of implanting neon ions into part or all of an arsenic-doped layer formed in advance on a part of a semiconductor substrate,
1. A method for manufacturing a semiconductor device having a high resistance layer, comprising the step of controlling the resistance value by heat treatment at a high temperature after this step.