JPS588160B2 - Method for manufacturing multilayer printed wiring board - Google Patents
Method for manufacturing multilayer printed wiring boardInfo
- Publication number
- JPS588160B2 JPS588160B2 JP12569378A JP12569378A JPS588160B2 JP S588160 B2 JPS588160 B2 JP S588160B2 JP 12569378 A JP12569378 A JP 12569378A JP 12569378 A JP12569378 A JP 12569378A JP S588160 B2 JPS588160 B2 JP S588160B2
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- prepreg
- multilayer printed
- manufacturing multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
本発明はプリプレグを介して積層した多層印刷配線板の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer printed wiring board laminated with prepregs interposed therebetween.
従来の一般的な多層印刷配線板の構造を第1図に示す。The structure of a conventional general multilayer printed wiring board is shown in FIG.
夫々表面層を形成する片面銅張積層板(印刷配線板)3
,3間には中間層5を形成する両面銅張積層板(印刷配
線板)5とプリプレグ6が交互に積み重ねられる。Single-sided copper-clad laminate (printed wiring board) 3 forming a surface layer, respectively
, 3, double-sided copper-clad laminates (printed wiring boards) 5 and prepregs 6 forming an intermediate layer 5 are alternately stacked.
中間層5は図においては一枚しか示してないが一般には
多数枚をプリプレグ6と交互に積層する。Although only one intermediate layer 5 is shown in the figure, generally a large number of intermediate layers 5 are laminated alternately with prepregs 6.
プレプリグ6はスペーサの役目も有するため一般には各
中間層間及び表面層と中間層間に2枚ずつ配置される。Since the prepregs 6 also serve as spacers, two prepregs 6 are generally arranged between each intermediate layer and between the surface layer and the intermediate layer.
これら表面層、中間層及びプリプレグの相対位置決めは
上下の金型2,2の基準ピン1,1によってなされる。The relative positioning of the surface layer, intermediate layer and prepreg is done by reference pins 1, 1 of the upper and lower molds 2, 2.
即ち、下方表面層3、プリプレグ6、中間層5、プリプ
レグ6、・・・・・・上方表面層3を順次基準ピン1に
嵌め込んでいけばよい。That is, the lower surface layer 3, the prepreg 6, the intermediate layer 5, the prepreg 6, . . . the upper surface layer 3 may be fitted into the reference pin 1 in this order.
尚、7,7は金型2,2が樹脂で汚れるのを防止する離
型フイルムである。Incidentally, reference numerals 7 and 7 are release films that prevent the molds 2 and 2 from being contaminated with resin.
両表面層3及び中間層5は積層プレス(図示せず)で両
金型2,2を加熱加圧することによりそれらの間に介在
させたプリプレグ6によって一体的に固着され、斯うし
て多層印刷配線板を構成する。Both surface layers 3 and intermediate layer 5 are integrally fixed by prepreg 6 interposed between them by heating and pressing both molds 2, 2 with a lamination press (not shown), and thus multilayer printing is performed. Configure the wiring board.
表面層と中間層あるいは中間層同士を接着するプリプレ
グ6は一般にはガラス布にエポキシ樹脂等の未硬化樹脂
を含浸塗布して構成される。The prepreg 6 for adhering the surface layer and the intermediate layer or the intermediate layers to each other is generally constructed by impregnating and coating a glass cloth with an uncured resin such as an epoxy resin.
プリプレグ単体を加熱すると未硬化樹脂が収縮硬化して
その両面の印刷配線板を接着するのであるがこの収縮硬
化はプリプレグ及び多層印刷配線板の寸法安定性を悪く
するものである。When a single prepreg is heated, the uncured resin shrinks and hardens to bond the printed wiring boards on both sides, but this shrinkage and hardening deteriorates the dimensional stability of the prepreg and multilayer printed wiring board.
即ちプリプレグは収縮硬化するときにそれに接着してい
る印刷配線板も一緒に引っ張るような形になりその結果
印刷配線板にも寸法ずれが生じることになるのである。That is, when the prepreg shrinks and hardens, it pulls together the printed wiring board that is adhered to it, resulting in dimensional deviations in the printed wiring board as well.
その結果、印刷配線板にパターン配線された導体パター
ンの例えばランド部が2つの層間で位置ずれを生じ、本
来ならばランド部中心に穿けられるべきスルーホールが
例えば2層目ではランド部中心からはずれてしまいその
一部がランド部の形成されていない場所に位置するよう
になってしまうことがあった。As a result, for example, the land portion of the conductor pattern patterned on the printed wiring board may be misaligned between the two layers, and a through hole that should normally be drilled at the center of the land may be deviated from the center of the land portion in the second layer, for example. As a result, a part of the land portion may end up being located in a place where no land portion is formed.
このことはランド部から外れた部分のスルーホールには
電気的導通が断たれることを意味するのでその位置にた
またま導体パターンが配線されていたような場合には断
線と同じ結果になり看過し得ない欠点となる。This means that electrical continuity is broken in the through-hole that is outside the land area, so if a conductor pattern happens to be wired at that position, the result will be the same as a disconnection and should be overlooked. This is a disadvantage that cannot be gained.
このように印刷配線板の位置ずれはそれ自身の収縮によ
るものではなくプリプレグの収縮に牽引されておこるも
のである。In this way, the misalignment of the printed wiring board is caused not by its own shrinkage, but by the shrinkage of the prepreg.
更にまたこの印刷配線板の位置ずれを測定してみると当
然のことながら中央のランド部のみならず縁部近傍の基
準ピン孔の部分でも生じており基準ピン孔を原点位置に
戻すとすると最大変位量はこれらの総和となって表われ
る。Furthermore, when we measured the positional deviation of this printed wiring board, we found that it occurred not only at the central land but also at the reference pin hole near the edge, and when the reference pin hole was returned to its original position, the maximum The amount of displacement is expressed as the sum of these.
また種々の実験の結果プリプレグを基準ピンから自由、
即ちプリプレグを基準ピンに差し込まないようにすると
位置量がはるかに小さくなることが確かめられた。In addition, as a result of various experiments, the prepreg was freed from the reference pin,
That is, it was confirmed that if the prepreg was not inserted into the reference pin, the position amount would be much smaller.
これはプリプレグを基準ピンの束縛から自由にすること
により却って自由に収縮し印刷配線板に与える影響が小
さくなりひずみや局所的変位となって現われることがな
いため及びプリプレグの面積が小さくなる程印刷配線板
に及ぼす牽引力が小さくなるためと考えられる。This is because by freeing the prepreg from the restraints of the reference pins, it will shrink freely and have less influence on the printed wiring board, and will not appear as distortion or local displacement. This is thought to be because the traction force exerted on the wiring board becomes smaller.
本発明は上述の如き特徴にもとづいてプリプレグの一部
を欠除して基準ピンにかからないようにしそれにより印
刷配線板の寸法精度を高めようとするものである。The present invention is based on the above-mentioned characteristics by removing a part of the prepreg so that it does not touch the reference pin, thereby improving the dimensional accuracy of the printed wiring board.
本発明によれば第2図に示す如くプリプレグ16には基
準ピン1は差し込まれていない。According to the present invention, the reference pin 1 is not inserted into the prepreg 16 as shown in FIG.
この目的のためにプリプレグ16は例えば第3図に示す
如く従来の基準ピン孔18を含む4辺を破線17で示す
如く切除するかあるいは第4図に示す如く基準ピン孔1
8′の部分17′だけを切除するかして基準ピン1にか
からないようにする。For this purpose, the prepreg 16 may be cut off at four sides including the conventional reference pin hole 18 as shown in broken lines 17 as shown in FIG.
Only the portion 17' of 8' is removed so that it does not touch the reference pin 1.
プリプレグ16は基準ピン1から解放されたためにその
位置決め用として位置決めピン9を設けてもよいがその
場合にはピン孔20はできるだけプリプレグの中心近傍
に位置させてプリプレグの自由収縮になるべく影響を与
えないようにする。Since the prepreg 16 is released from the reference pin 1, a positioning pin 9 may be provided for positioning it, but in that case, the pin hole 20 should be located as close to the center of the prepreg as possible to influence the free contraction of the prepreg as much as possible. Make sure not to.
位置決めピン9はなくてもよい。The positioning pin 9 may not be provided.
ここで留意すべきことは印刷配線板の寸法基準位置は常
に基準ピン1の位置を原点として測定されるのであり従
って位置決めピン9は基準寸法の測定に際しては何ら寄
与せず、従って重要なのは特に基準ピン1の近傍の寸法
ずれであるということである。It should be noted here that the dimensional reference position of the printed wiring board is always measured using the position of the reference pin 1 as the origin, and therefore the positioning pin 9 does not contribute in any way to the measurement of the reference dimension. This means that it is a dimensional deviation in the vicinity of pin 1.
プリプレグの一部が第3図あるいは第4図に示す如く欠
除されているので印刷配線板はプリプレグの硬化収縮時
に少くとも基準ピン1の近傍位置ではプリプレグにつら
れて引っ張られることもなく従ってそれだけ寸法ずれも
小さくなり、冒頭に述べた如き問題も解決される。Since a part of the prepreg is removed as shown in FIG. 3 or 4, the printed wiring board is not pulled by the prepreg at least in the vicinity of the reference pin 1 when the prepreg hardens and contracts. Dimensional deviations are also reduced, and the problems mentioned at the beginning are solved.
本発明の目的からはプリプレグの切除部分はできるだけ
大きい方が好ましいがプリプレグ本来の接着層としての
機能からは徒らにプリプレグの面積を縮少することもで
きないのでこれらの点を勘案して適当に決められること
になる。For the purpose of the present invention, it is preferable that the removed portion of the prepreg be as large as possible, but considering the function of the prepreg as an adhesive layer, it is not possible to reduce the area of the prepreg needlessly, so the cutout portion of the prepreg should be made as large as possible, taking these points into consideration. It will be decided.
第1図は従来の典型的な多層印刷配線板の製造方法を示
す図、第2図は本発明に係る製造方法を示す第1図と同
様の図、第3図は本発明において用いられるプリプレグ
の斜視図、第4図は第3図の変形を示す図。
1・・・・・・基準ピン、3,5・・・・・・印刷配線
板、6,16・・・・・プリプレグ。FIG. 1 is a diagram showing a typical conventional method for manufacturing a multilayer printed wiring board, FIG. 2 is a diagram similar to FIG. 1 showing a manufacturing method according to the present invention, and FIG. 3 is a diagram showing a prepreg used in the present invention. FIG. 4 is a perspective view showing a modification of FIG. 3. 1... Reference pin, 3, 5... Printed wiring board, 6, 16... Prepreg.
Claims (1)
準ピンにより位置合わせをしながら交互に積層して多層
印刷配線板を製造するに際し,上記プリプレグの少くと
も基準ピンに対応する部分を切除して上記基準ピンは印
刷配線板のみに差し込まれるようにしたことを特徴とす
る多層印刷配線板の製造方法。1. When manufacturing a multilayer printed wiring board by alternately stacking a plurality of printed wiring boards and prepregs while aligning them using reference position reference pins, at least the portion of the prepreg that corresponds to the reference pins is cut out. A method for manufacturing a multilayer printed wiring board, characterized in that the reference pin is inserted only into the printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12569378A JPS588160B2 (en) | 1978-10-14 | 1978-10-14 | Method for manufacturing multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12569378A JPS588160B2 (en) | 1978-10-14 | 1978-10-14 | Method for manufacturing multilayer printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5553495A JPS5553495A (en) | 1980-04-18 |
| JPS588160B2 true JPS588160B2 (en) | 1983-02-14 |
Family
ID=14916355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12569378A Expired JPS588160B2 (en) | 1978-10-14 | 1978-10-14 | Method for manufacturing multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS588160B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6313395A (en) * | 1986-07-03 | 1988-01-20 | 日本電気株式会社 | Manufacture of multilayer printed interconnection board |
-
1978
- 1978-10-14 JP JP12569378A patent/JPS588160B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5553495A (en) | 1980-04-18 |
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