JPS588175B2 - Multiplex signal transmitter/receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is characterized in that a primary winding is energized by a three-phase AC power supply, and a secondary winding has an intermediate tap. A transformer device that obtains a main signal AC power source and three sub signal AC power sources with their phases reversed by 180 degrees, and one positive and negative half wave of the main signal AC power source and the sub signal AC power source. By clipping the positive and negative half-waves of the sub-signal AC power supply and the main signal AC power supply, which have a phase difference of 60 degrees, and extracting the overlapping parts of both waveforms, the waveforms have the same polarity and do not overlap. The present invention relates to a multiple signal transmitting/receiving device in which a transmitting device and a receiving device are each equipped with a diode matrix circuit that generates a plurality of signal waveforms that are positively and negatively symmetrical. A selection switch device that selects the waveform signals from the transmission device and a transmission circuit that transmits the waveform signals from the selection switch device as the transmission signals are provided, and the reception device is provided with the transmission signals transmitted from the transmission device and the transmission circuit. A receiving circuit that individually compares the signal waveform from its own diode matrix circuit and receives it when both exist, and a zero point of each signal transmitted from the transmitting device and each signal waveform from its own diode matrix circuit. By installing an abnormality detection circuit that detects the time width between the two and causes the response device to respond when the time width exceeds a predetermined value, it is possible to eliminate the need for any of the three-phase AC power supply and main/sub signal AC power supply. It is an object of the present invention to provide a multiplex signal transmitting/receiving device that can reliably detect when there is a mismatch or when a diode in a diode matrix circuit fails, thereby preventing a receiving circuit from receiving erroneous signals.

An embodiment of the present invention will be described below with reference to the drawings.

First, the transmitting device 1 will be described according to FIGS. 1 and 2.

That is, 2, 3, and 4 are power terminals connected to a three-phase or current power source (not shown) consisting of R, S, and T phases, and 5, 6, and 7 are first, second, and third terminals constituting the transformer device. transformers, and the primary windings 5P of these transformers 5, 6 and 7 are
6P and 1P are connected between the power terminals 2 and 3, between 3 and 4, and between 4 and 2, respectively, and intermediate taps 5M, 6M and 7 are connected for phase inversion of the secondary windings 5S, 6S and 7S.
Ground M.

Then, both ends of the secondary winding 5S of the first transformer 5 are connected to the signal power supply terminals 8 and 9, and the secondary winding 6S of the second transformer 6 is connected to the signal power supply terminals 8 and 9.
Both ends of the secondary winding 7S of the third transformer 7 are connected to the signal current power terminals 10 and 11, and both ends of the secondary winding 7S of the third transformer 7 are connected to the signal current power terminal 1.
2 and 13, respectively, and the signal AC power supply circuit 14 is constituted by the above.

15 is a diode matrix circuit, and 16 to 21 are intermediate terminals.The diode matrix circuit 15 will be described in detail below.The signal power supply terminal 8 and the intermediate terminal 1
A resistor 22 and polarity diodes 23 and 24 that pass the positive half wave are connected in series between the terminal 6 and the positive half wave line 25 to form a positive half wave line 25 which is a half wave line with one polarity. A resistor 26 and polarity diodes 27 and 28 that pass a negative half wave are connected in series between the terminal 17 to form a negative half wave circuit 29 which is the other polarity half wave circuit. A positive half-wave electric line 3 consisting of a resistor 30 and diodes 31 and 32 is connected between the AC power supply terminal 10 and the intermediate terminal 18.
3, a negative half-wave circuit 37 consisting of a resistor 34 and diodes 35 and 36 is connected between the signal AC power terminal 11 and the intermediate terminal 19, and a resistor 38 is connected between the signal AC power terminal 12 and the intermediate terminal 20. , a positive half-wave circuit 41 consisting of diodes 39 and 40, and a signal AC power supply terminal 13 and an intermediate terminal 21.
A negative half-wave circuit 45 consisting of a resistor 42 and diodes 43 and 44 is formed between the two.

And each of these positive and negative half-wave electric circuits 25, 29, 33,
In order to clip voltages 37, 41 and 45 with a phase difference of 60 degrees from each other through forward diodes,
The signal AC power supply terminals 11 and 10 are distributed and connected to the positive and negative half-wave circuits 25 and 29 through forward direction diodes 46 and 41, respectively, and the positive and negative half-wave circuits 33 and 37 has signal AC power terminals 13 and 12.
are distributed and connected via diodes 48 and 49, respectively, and a signal AC power supply terminal 9 is connected to the positive and negative half-wave circuits 41 and 45.
and 8 are distributed and connected via diodes 50 and 51, respectively.

52 is a selection switch device having six selection switches 53 to 58;
One end is connected to the intermediate terminals 16 to 21, and the other ends of the selection switches 16, 18 and 20 are connected in common,
The common connection point is connected to the base of the NPN transistor 60 of the transmission circuit 59, and the other ends of the selection switches 17, 19 and 21 are connected in common, and the common connection point is connected to the base of the NPN transistor 60 of the transmission circuit 59. Connect to the base of

Regarding the transmission circuit 59, resistors 62 and 63 are connected in series between the emitters of the transistors 60 and 61, the common connection point of the resistors 62 and 63 is grounded, and the collector of the transistor 60 is connected to the ground. It is connected to a positive (+) DC power supply terminal 64, and the collector of the transistor 61 is connected to a negative (-) DC power supply terminal 65.

66 is an NPN type transistor whose emitter is grounded, and its collector is connected to the base of the transistor 60.

67 is a PNP type transistor whose emitter is grounded, and its collector is connected to the base of the transistor 61.

68 is an amplifier for configuring the high frequency oscillator 69, one input terminal of which is grounded through a resistor 70 and branched into two through a resistor 71, the first branch end of which is connected to the output terminal; The second branch end is grounded through resistors 72 and 73 in series.

Further, the other input terminal of the amplifier 68 is grounded via a capacitor 74 and connected to the common connection point of the resistors 72 and 73.

Furthermore, the output terminal of the amplifier 68 is connected to each of the transistors 66 and 67 through diodes 75 and 76 of the polarity shown, respectively.

Note that 77 and 78 are positive and negative DC power supply terminals of the amplifier 68.

Then, the valley emitters of the transistors 60 and 61 are connected to one of the transmission terminals 82 and 83 through diodes 80 and 81 of the illustrated polarity constituting an OR circuit 79, respectively, and connected to the other transmission terminal. 83 is grounded, and one transmission terminal 82 is connected to a transmission line 84 which is a transmission path.
Connect to.

Now, to describe the receiving device 85 according to FIGS. 3 and 4, since the configurations of the signal AC power supply circuit and the diode matrix circuit are the same as those of the transmitting device 1, a subscript a is added to the reference numerals of each part of the transmitting device 1. By doing so, it will be shown that they are the same, and the explanation will be omitted, and only the different parts will be explained.

86, 87, and 88 are current transformer power supply terminals 8a for each signal,
9a, 10a, 11a, 12a, 13a, and to explain one receiving circuit 86 now, 89 is an NPN type transistor whose emitter is grounded via a resistor 90. At the same time, it is connected to the gate of SCR (thyristor) 91, and the SCR
The cathode of 91 is grounded, and the anode is connected to the signal AC power supply terminal 8a via the receiving relay 92.

93 is a PNP type transistor whose emitter is grounded via a resistor 94 and connected to the gate of a PUT (programmed unijunction transistor) 95, whose anode is grounded and whose cathode is connected to a signal via a receiving relay 96. Connect to the utility power supply terminal 9a.

The bases of the transistors 89 and 93 are connected to the intermediate terminals 16a and 17a through forward diodes 97 and 98, respectively, for the base current, and
Receiving terminals 101 and 1 are connected to each collector through forward diodes 99 and 100, respectively, for the collector current.
02, and the other receiving terminal 102 is grounded.

Then, the receiving terminal 101 is connected to the transmission line 84.

Note that 103 and 104 are circuits consisting of resistors and capacitors, and these are for absorbing surges of the receiving relays 92 and 96 and preventing vibrations.

The above description is about the receiving circuit 86, but since the other receiving circuits 87 and 88 have exactly the same configuration, their explanation will be omitted.

However, in the receiving circuits 87 and 88, receiving relays 105 and 106 corresponding to the receiving relay 92 and receiving relays 107 and 108 corresponding to the receiving relay 96
is illustrated.

109 is a positive DC power supply terminal connected to the positive pole of the DC power supply whose negative pole is grounded, and there is an abnormality detection relay 11 to be described later.
The bus bar 111 is connected through the normally closed contact 110b of 0, and the receiving relays 92, 96, 1 are connected between the bus bar 111 and the ground.
Normally open contacts 92a, 9 of 05, 107, 106 and 108
A series circuit of 6a, 105a, 107a, 106a, and 108a and a load (not shown) corresponding to each of the above-mentioned receiving relays is sequentially connected in parallel, thereby forming a load circuit 112.

113 is an abnormality detection circuit, which will be described in detail below.

That is, 114 is a diode whose anode is connected to the receiving terminal 101 and whose cathode is connected to the terminal 116 via an integrator 115.

Diodes 117, 118, and 119 have their anodes connected to the intermediate terminals 16a, 18a, and 20a, respectively, and their cathodes commonly connected to the terminal 116.

120 is a diode whose cathode is connected to the receiving terminal 1
01, and the anode is connected to terminal 1 through the integrator 121.
Connect to 22.

Diodes 123, 124, and 125 have their cathodes connected to the intermediate terminals 17a, 19a, and 21a, respectively, and their anodes commonly connected to the terminal 122.

The terminal 116 is connected to a diode 126 with the polarity shown.
The terminal 122 is connected to a terminal 127 via a light emitting diode 128 and a resistor 129 of the polarity shown in the figure, which are connected in series.

130 is a positive DC power supply terminal whose negative pole is connected to the positive pole of a DC power supply that is grounded, and to which a bus bar 131 is connected.

A phototransistor 132 is placed close to the light emitting diode 128, and its collector is connected to the bus bar 131, and its emitter is connected to the terminal 127 via a diode 133 having the polarity shown.

134 and 135 are NPN transistors whose emitters are grounded, and the base of the transistor 134 is connected to terminal 1.
27, the collector is branched into two, the first branch end is connected to the bus 131 via the resistor 136, the second branch end is connected to the base of the transistor 135, and the collector of the transistor 135 is connected to the base of the transistor 135. is connected to terminal 137.

138 and 139 are resistors and capacitors connected in series between the bus bar 131 and the ground to constitute the time constant circuit 140, and the common connection point between them is branched into two, and the first branch end is connected to the terminal 137. and connect the second branch end to PU, T
141 anode.

Further, the cathode of the PUT 141 is branched into two, the first branch end is grounded via the capacitor 142, the second branch end is connected to the terminal 143, and the gate is connected between the bus bar 131 and the ground. It is connected to a common connection point of resistors 144 and 145 connected in series.

146 is an NPN type transistor for operating the abnormality detection relay 110 as a response device, its base is connected to the terminal 143, the collector is connected to the bus bar 131 via the abnormality detection relay 110, and the emitter is grounded. do.

Next, the fifth section regarding the operation of this embodiment configured as described above will be explained.
To explain with reference to FIG. 6 and FIG.
and 4, the signal AC power terminals 8, 10 and 12 correspond to the R, S and T phases of the three-phase AC power supply, respectively, as shown in Figure 5 A, B and C. 120
AC power supplies for the first, second and third main signals which are out of phase by a degree are obtained, and the AC power supplies for the eleventh second and third main signals are connected to the signal AC power terminals 9, 11 and 13. First, second and third AC power supplies for sub-signals as shown in FIG. 5 D, E and F in which the phases of A, B and C are inverted by 180 degrees are obtained.

These 11th second and third main signal current transformer power supplies A, B, and C are connected to The sub-signal AC power supplies D, E, and F are divided by negative half-wave circuits 29, 37, and 45, respectively, so that the negative half-wave passes through them, and the positive half-wave circuits 25, 33, and 41 have a phase lead of 60 degrees. The sub signal AC power supplies E, F and D are diodes 46 and 48.
and 50, and the main signal AC power supplies B, C, and A whose phase is advanced by 60 degrees are applied to the negative half-wave circuits 29, 37, and 45 via diodes 47, 49, and 51, and a clipping effect occurs. As a result, the overlapping portions of both waveforms are output to the output terminals 16, 18 and 20 and 17, 19 and 21 as shown by the diagonal lines in FIG. 5 and a in FIG. 6, so that the waveforms have the same polarity and do not overlap. Six approximately triangular signal waveform voltages V1, V2, V3, and V4 with positive and negative symmetry
, ■5, and V6 are generated, and these are sent to the transmission circuit 59 when the corresponding one of the selection switches 53 to 58 is closed.

Then, the signal waveform voltage sent to the transmission circuit 59 is separated into positive and negative signals, the positive signal waveform voltage is applied to the base of the transistor 60, and the negative signal waveform voltage is applied to the base of the transistor 60.
Added to the base of 1.

On the other hand, the high frequency oscillator 69 of the transmission circuit 59 generates positive and negative oscillation outputs as shown in FIG.
6 and 67 bases, respectively.

Therefore, when the high frequency oscillator 69 generates a negative oscillation output, the transistor 67 is on and the transistor 66 is off, and conversely, when the high frequency oscillator 69 generates a positive oscillation output, the transistor 66 is on and the transistor 67 is off. Positive and negative signal waveform voltages applied to the bases of transistors 60 and 61 are carved and alternately extracted according to the oscillation output, and these are combined via OR circuit 79 and sent to transmission terminal 82.

As a result, for example, when all the selection switches 53 to 58 are closed simultaneously, intermittent divided waveform voltages V1' to V6' are sent to the transmission terminal 82 as shown in FIG. 6C, and these are used as the transmission signal. The transmission line 84 is the same transmission line as
It is transmitted to the receiving device 85 via.

On the other hand, in the receiving device 85 as well as in the transmitting device 1, each intermediate terminal 16 is connected by a diode matrix circuit 15a.
Since signal waveform voltages ■1 to V6 similar to those shown in FIG. 5 are generated at a to 21a, for example, the selection switch 5
3, the positive divided waveform voltage V1' is transmitted to the transmitting terminal 82.
, 83 to the transmission line 84, and this is transmitted to the receiving terminal 10.
1,102, at this time transistor 8
9 has a signal waveform voltage V1 from the intermediate terminal 16a to its base.
is applied and turned on, the transmitted divided waveform voltage ■1' is applied to the gate of the SCR 91 via the diode 99 and between the collector and emitter of the transistor 89, turning it on, and thereby the receiving relay 92 is turned on. The SCR91 is activated by the positive half-wave voltage from the signal power supply terminal 8a.
is energized and operated to close the normally open contact 92a,
This means that it has been received.

For example, if the selection switch 54 is closed, the negative divided waveform voltage V4' is transmitted, and at the same time, the transistor 93 receives the signal waveform voltage V4' from the intermediate terminal 17a to its base.
4 is applied and turns on, PUT 95 also turns on because its gate is negative and its anode is positive, and as a result, the receiving relay 96 is energized by the negative half-wave voltage from the signal power supply terminal 9a and operates. to close the normally open contact 96a,
This means that it has been received.

Thereafter, in the same manner, other divided waveform voltages V2', V3', V
5, and V6' are also connected to separate receiving relays 105, 1, respectively, in response to the closing of selection switches 55, 57, 56, and 58, respectively.
06, 107 and 108.

Next, considering the case where the selection switches 53 and 54 corresponding to the signal waveform voltages V1 and V4 are selectively closed at the same time, the signal waveform voltages V1 and V4 have positive and negative symmetry within the same phase. If these are simply combined, they will cancel each other out and become zero (0), so there is a problem that they cannot be simultaneously transmitted through the same transmission line 84.

However, in this embodiment, the signal waveform voltage V1
and V4 are chopped in accordance with the oscillation output of the high frequency oscillator 68 and extracted alternately between positive and negative to obtain divided waveform voltages V1' and V4'.
Therefore, these divided waveform voltages V0' and V4
' Even if they are combined through the OR circuit 79, they will not be canceled out. Therefore, even if the same transmission line 84 is used, the receiving relays 92 and 96 corresponding to the signal waveform voltages V1 and V4 will not be canceled.
can be received simultaneously.

By the way, as in this embodiment, AC power supplies A to C for main signals and AC power supplies D to F for sub signals are obtained from Sanwa AC power supply,
Add power supplies E, F, and D for sub-signals with a 60 degree phase difference to the positive half-waves of AC power supplies A, B, and C for main signals, and add them to the negative half-waves of AC power supplies D, E, and F for sub-signals. When the signal waveform voltages V1 to 6 are obtained by adding and clipping main signal AC power supplies B, C, and A that are 60 degrees different in phase, for example, one of the diodes 46 to 51 for clipping If even one of them fails and becomes cut off, the clipping effect will no longer occur, and the positive or negative half-wave voltage of the positive or negative half-wave line that should be clipped will remain as it is in the transmission circuit 59 or the receiving circuits 86 to 88. Therefore, an unnecessary receiving circuit will receive the signal incorrectly.

For example, on the transmitting device 1 side, the diode 46 for adding and clipping the sub-signal AC power source E to the positive half-wave circuit 25 that passes the positive half wave of the main signal AC power source A fails and becomes cut off. In this case, since the clipping effect of the diode 46 is eliminated, a positive half wave of the main signal AC power supply A is generated at the intermediate terminal 16.

Therefore, in order to transmit the signal waveform voltage V1, the selection switch 5
When 3 is closed, not only the signal waveform voltage V1 but also the signal waveform voltage V2 is transmitted, and this is supported even though the selection switch 55 corresponding to the signal waveform voltage 2 is not closed. This will cause the receiving relay 105 of the receiving device 85 to malfunction.

Such an abnormality is caused not only by a faulty cutoff of the diode for clipping, but also by an open phase of any of the Sanwa AC power supplies, AC power supplies A to F for main and sub-signals, or a faulty conduction of the diode in the diode matrix circuit 15. This also occurs at times, and of course it can also occur on the receiving device 85 side.

In this embodiment, in order to detect such an abnormality, the abnormality detection circuit 113 operates as follows.

That is, the positive divided waveform voltages V1' to V3' transmitted by the transmission line 84 are connected to the diode 114 and the integrator 1.
15 and the positive signal waveform voltages V1 to V3 from the diode matrix circuit 15a are connected to the diode 117.
The divided waveform voltages ■4' to ■ applied to the terminal 116 via the terminals 119 and further transmitted by the transmission line 84
6' is applied to the terminal 122 via the diode 120 and the integrator 121, and the negative signal waveform voltages V4 to V6 from the diode matrix circuit 15a are applied to the terminal 122 via the diodes 123 to 125.

Therefore, signal waveform voltages 1 to 3 as shown in FIG. 6a are always generated at the terminal 116, and signal waveform voltages V4 to V6 as shown in FIG. 6a are always generated at the terminal 122.

In this case, the divided waveform voltages V1' to V from the transmission line 84
6' is an intermittent signal voltage, which is passed through the integrator 11.
5 and 121, the signal waveform voltages are converted into continuous signal voltages having a time width approximately equal to the time width T between zero points of each signal voltage, and henceforth, for convenience, the signal waveform voltages will be described as signal waveform voltages V1 to V6.

Therefore, the signal waveform voltages V1 to V3 at the terminal 116 are applied to the terminal 127 via the diode 126, and the signal waveform voltages V1 to V3 at the terminal 1
22 signal waveform voltages V4 to V6 are the light emitting diodes 12.
8 and the phototransistor 132, and is applied to the terminal 127 via the diode 133, so that the main signal AC power supply A is connected to the terminal 121.
Signal voltages corresponding to signal waveform voltages V1 to V3 having a time width T are always generated during a period of 1 Hz.

Since these signal voltages are applied to the base of the transistor 134, the transistor 134 is turned on only during the period when the signal voltage is present, and therefore the transistor 135 is turned on.
is turned off, and capacitor 139 is charged via resistor 138 while transistor 135 is off.

In this case, when the capacitor 139 is charged for a period of the time width T of each signal waveform voltage, the time constant circuit 140 is set so that the voltage between its terminals becomes equal to or lower than the operating voltage Va of the PUT 141 given by the resistors 144 and 145. If a constant is set, each signal waveform voltage V1 to V is set before the voltage between the terminals of the capacitor 139 reaches the operating voltage Va during normal operation.
The signal voltage corresponding to 3 becomes zero, so the transistor 134 is turned off, the transistor 135 is turned on, and the charge in the capacitor 139 is discharged through the transistor 135 almost instantaneously.

As a result, under normal conditions, the capacitor 139 is repeatedly charged and discharged with a time width T, and the voltage at the terminal 137 becomes as shown in FIG. 6d.

Therefore, the PUT 141 is off and the transistor 146 is also off, the relay 110 is not energized and returns to close the normally closed contact 110b, and the load circuit 112 receives the signals from the receiving relays 92, 96, 105 to 108. Based on the operation, energization/disconnection control of the corresponding load is performed.

For example, if the clipping diode 46 of the diode matrix circuit 15 on the transmitter 1 side fails and becomes cut off, a positive half-wave voltage of the main signal AC power source A is generated at the intermediate terminal 16.

Therefore, in order to transmit the signal waveform voltage V1, the selection switch 5
3 is selectively closed, a signal voltage corresponding to the signal waveform voltage V1 is applied to the terminal 127 on the receiving device 85 side, the transistor 134 is turned on, the transistor 135 is turned off, and the capacitor 139 is charged.

When the time width T of the signal waveform voltage V1 has elapsed, the signal waveform voltage V1 becomes zero under normal conditions, but as described above, the signal waveform voltage from the transmission line 84 becomes Since it is a half-wave voltage, the signal voltage at the terminal 127 does not become zero even after the time period T has elapsed, and the capacitor 139 continues to be charged as shown by the two-dot chain line in FIG. When the voltage between its terminals reaches the operating voltage Va (
Time t) The PUT 141 is turned on, and the capacitor 142 is charged almost instantaneously and gradually starts discharging.

Therefore, the voltage at terminal 143 becomes as shown by the two-dot chain line in FIG. 6e, transistor 146 is supplied with base current and turned on, energizing relay 110 to operate and opening normally closed contact 110b.

Thereby, the bus bar 111 of the load circuit 112 is disconnected from the DC power supply terminal 109.

The above is a case where the clip diode 46 of the diode matrix circuit 15 on the transmitting device 1 side fails and is cut off. However, if other diodes are broken off or made conductive due to a fault, the three-phase AC power supply, the AC power supply for primary and secondary signals Abnormality detection is performed in exactly the same manner even when any of A to F has an open phase, and of course, it is also detected when a similar abnormality occurs on the receiving device 85 side.

According to this embodiment, the signal waveform voltages V1 to V6 selected by the selection switch device 52 are extracted alternately between positive and negative according to the oscillation output of the high frequency oscillator 69 and transmitted as divided waveform voltages V1' to V6'. Since the signals are transmitted through the line 84, even if the signal waveform voltages are symmetrical in positive and negative within the same phase, they can be simultaneously transmitted through the same transmission line 84.

Further, an abnormality detection circuit 113 is provided on the receiving device 85 side to detect the time width T between the zero points of each signal waveform voltage transmitted from the transmission line 84 and each signal waveform voltage from the diode matrix circuit 15a of the receiving device 85. Since the relay 110 is activated when the detected value becomes larger than a predetermined value, if the diodes of the diode matrix circuits 15 and 15a of the transmitting device 1 and the receiving device 85 fail, the three-phase AC power supply or signal To be able to reliably detect a phase loss in any of the AC power supplies A to F for use, and to detect abnormalities in both the transmitting device 1 and the receiving device 85 with the same abnormality detection circuit 113. It is something that can be done.

Moreover, both the signal AC power supply circuit 14 on the transmitter 1 side and the signal AC power supply circuit 14a on the receiver 85 side,
Since the transformers 5 to 7 and 5a to 7a, which are energized by the same commercial power source, 3-phase AC power supply, are used to obtain the main signal current power supplies A to C and the sub signal AC power supplies D to F, respectively. , between the main signal AC power supplies A to C and the sub signal AC power supplies D to F on the transmitting device 1 side and the main signal AC power supplies A to C and the sub signal AC power supplies D to F on the receiving device 85 side. There is no phase shift, etc.
Therefore, the diode matrix circuit 15 on the side of the transmitter 1
The signal waveform voltages V1 to V6 obtained from the receiving device 85
The signal waveform voltages V1 to V6 obtained from the side diode matrix circuit 15a are reliably synchronized, and there is an advantage that the receiving operation in the receiving device 85 can be performed accurately.

In the above embodiment, the high-frequency oscillator 69 extracts the signal waveform voltages V1 to V6 on the transmitting device 1 side, either positive or negative, and transmits them as divided waveform voltages V1' to V6'. If it is not necessary to simultaneously transmit the signal waveform voltages using the same transmission line 84,
Instead of the transmission circuit 59, a simple transmission circuit may be constructed that synthesizes the signal waveform voltage from the selection switch device 52 and directly transmits it from the transmission line 84. In this case, the integrator of the abnormality detection circuit 113 115 and 121 are not required.

Further, in the above embodiment, three single-phase transformers 5, 5a to 7, 7a are used in combination as the transformer device.
Alternatively, a single three-phase transformer may be used, each having a center tap on its secondary winding.

In addition, the present invention is not limited to the embodiments described above and shown in the drawings, and may be modified as appropriate without departing from the scope of the invention, for example, the relay 110 may be used to operate an alarm device such as a lamp. Of course, it can be carried out as well.

As described above, the present invention is capable of reliably detecting an open phase in any of the three-phase AC power supply and the signal AC power supply, and in the event that a diode in the diode matrix circuit fails. A multiplex signal transmitting/receiving device that can accurately receive signals can be provided.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, in which Fig. 1 is an electrical circuit diagram of a transmitting device, Fig. 2 is an electrical circuit diagram of a transmission circuit, Fig. 3 is an electrical circuit diagram of a receiving device, and Fig. 4 is an electrical circuit diagram of an abnormality detection device. FIG. 5 is a signal waveform diagram, and FIGS. 6a to 6e are waveform diagrams of various parts for explaining the operation. In the drawing, 1 is a transmitting device, 5 and 5a are first transformers, and 6
and 6a is a second transformer, 7 and 7a are third transformers,
14 and 14a are signal AC power supply circuits, 15 and 15a
are diode matrix circuits, 25, 33 and 41 are positive half-wave circuits, 29, 37 and 45 are negative half-wave circuits, 52 is a selection switch device, 59 is a transmission circuit, 69 is a high frequency oscillator, 79 is an OR circuit, 84 85 is a receiving device, 86 to 88 are receiving circuits, 110 is a relay (
112 is a load circuit, 113 is an abnormality detection circuit, 140 is a time constant circuit, V1 to V6 are signal waveform voltages (
V1' to V6' indicate divided waveform voltages (transmission signals).

Claims (1)

[Claims] 1. The primary winding is energized by a three-phase AC power supply, the secondary winding has an intermediate tap, and the secondary winding has three main signal AC power supplies corresponding to the three-phase AC power supply, and these 18
A one-polarity half-wave consisting of a transformer device that obtains three sub-signal AC power supplies with the phases reversed by 0 degrees, and a polarity diode that allows only one of the positive and negative half-waves to pass through each of the main signal AC power supplies. each sub-signal AC power source is connected to the other polarity half-wave electrical circuit consisting of a diode having a polarity that allows only the other half-wave, positive and negative, to pass therethrough; By adding the sub-signal AC power supply and the main signal AC power supply, each with a phase difference of 60 degrees, to the polarity half-wave circuit through a diode in the forward direction and extracting the overlapping part of both waveforms, the waveforms can be made to overlap with the same polarity. A transmitting device and a receiving device each include a diode matrix circuit that generates a plurality of signal waveforms with positive and negative symmetry, and the transmitting device includes a selection switch that respectively selects the signal waveform from the diode matrix circuit. and a transmission circuit that transmits the signal waveform selected by the selection switch device as a transmission signal, and the receiving device receives the transmission signal transmitted from the transmission circuit and the transmission signal from its own diode matrix circuit. Detects the time width between the zero points of each signal waveform from the receiving circuit, each transmission signal from the transmission circuit, and the own diode matrix circuit when both are present by individually comparing the signal waveforms of 1. A multiplex signal transmitting/receiving device comprising: an abnormality detection circuit that causes a response device to respond when the detected value exceeds a predetermined value.