JPS588198B2 - Time division channel system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time division communication channel system in which the time switches required in the time division switching system are economically configured and are mainly based on a two-stage configuration of the time switches.

Conventionally, a large-capacity time-division communication path uses a time switch (hereinafter abbreviated as a T-switch).

) and space switch (hereinafter abbreviated as S switch).

), e.g. T-S-T. S-T-S,T
-S-S-S-S-T, etc., because it was realized by
The number of parts is large, and the control program and control circuit for controlling the communication path are complicated, which impairs economic efficiency. Also, since it uses an S switch composed of logic gates, it cannot be used as a general-purpose LSI (Large-Scale Integrated Circuit). It had the disadvantage of having little affinity for

The present invention is widely used in main memory devices in electronic computers, etc.
It provides a time-division communication path system that is highly compatible with highly versatile LSI memory elements.The time-division communication path is configured only with T-switches, and multiple storage devices are used inside the T-switch. The sequential access side accesses the plurality of blocks in parallel.The purpose of this is to reduce the number of memory element peripheral circuits and to simplify communication path control.

Examples will be described in detail below.

FIG. 1 is an explanatory diagram of a first embodiment showing the basic part of the present invention, in which M1 to n are storage device blocks, Di, D0, Add, WE, and BS are input/output terminals of the storage device block. Data input, data output, address input, write enable and block select terminals respectively, HWLI is input highway, HWJO1~n are output highways, OR1~n are OR gates, SEL is selector, DEC is decoder, R/W is Read/write control signal, HM is holding memory, CTR is counter, SQ is counter, RN is holding memory HM output and random address,
L1-n are latch circuits, Rp is a read pulse, WEp is a write pulse, CLK is a clock signal, and INV is an inversion circuit.

FIG. 2 shows the operating waveforms in FIG. 1, where the same symbols as in FIG. 1 represent waveforms at the same locations, and γ is the input highway HWLI.
The width of one time slot of A, B. C and F are the contents of each times field of the input highway HWLI, and U. V. X is the content of each time slot of the output highway HWJO1 to n, and the description Add;P(U) in the waveform of M1 to n represents that the address is P and the stored content is U, and the same description follows. is the same as above, and M in waveform RN
The descriptions 1 to α represent addresses α of the storage device block M1, and the following descriptions are the same as above, and p, p+1, . . . in the waveform SQ represent addresses common to all storage device blocks M1 to n. represent.

Next, the operation will be explained according to FIGS. 1 and 2.

The input highway HVVLI is K-multiplexed, and FIG. 2 mainly shows n time slots thereof.

Each piece of information on the input highway HWLI is written to the storage device at the position of the write pulse WBp at the write timing W (W side of the waveform R/W), and its address is random because the holding memory HM side is selected by the selector SEL. address (RN), and its random address R
The upper bits of N are decoded by the decoder DEC, and a signal appears at only one of the n output terminals at the output of the decoder DEC, and this signal corresponds to the block select (BS) of each storage device. Since the input is "1", the inverting circuit INV output connected to one terminal of the OR circuit becomes "0", and therefore only the BS terminal among the n storage device blocks is designated, and the output of the inverting circuit INV is "0" because the input is "1". Data is written only to the specified address.

This situation is illustrated by an arrow in FIG. 2, where information "A" on the input highway HWLI is written to address α of M1, the content of address α becomes "A", and "B" is written to address β of Mn. The contents of address β become 'B', and so on.

Here, α, β, . . . are address information including designations of M1 to Mn.

Next, to explain the read operation, when the R/W signal is at the "0" level, that is, at the read timing, the counter CTR side is selected as the address by the selector SEL;
N■ Output is “1” because the input is “0” level υ, D
Irrespective of the EC output, the BS of each memory device block is "1", and the outputs of all the memories are valid, and the memory outputs are input to the latch circuits L1 to L, and held by the read pulse Rp.

Since the read address does not use the lower bits corresponding to n of the counter CTR output, the same address is specified n times, and the read pulse Rp is placed at any position among these (after the long in the example in Figure 2) only once. It is only necessary that the write pulse WE
The period may be 1/n of p.

By the above operation, multiple memory device blocks can be read out in parallel with one read pulse Rp, and the portion marked with (d) in the R portion of the R/W signal in FIG. 2 is made empty. and K/n multiplexed output highway HWJ01~
The operation of separating n into n pieces can be performed at the same time.

In the description of the first embodiment described above, sequential access is used on the reading side, but it is obvious that similar features can be obtained even when sequential access is used on the writing side.

FIG. 3 shows, as a second embodiment, a configuration in which sequential access is used on the write side and random access is used on the read side.

In Figure 3, HWJI1 to HWJIn are input highways,
LO is an output highway, Rp' is a read pulse, which is generated successively corresponding to each time slot of HWLI, such as WEp in FIG. 2, and WEp' is a write pulse, which is generated by Rp as Rp in FIG. ' occurs 1/n times, L is a latch circuit, and other symbols are the same as those used in FIG.

FIG. 4 is an explanatory diagram of the third embodiment, in which a two-stage time-division communication channel is constructed by combining the first embodiment and the second embodiment, and Sp1 to n are The primary switches are the same as in Fig. 1, and the secondary switches Ss1 to Ss are the same as in Fig. 3.
s1 to n indicate the case where each is composed of 4 storage device blocks, and since the number of junctor highways between the primary switch and the secondary switch is equal to the number of storage device blocks of the primary and secondary switches, new Junctors between the primary and secondary switches can be constructed without additional circuitry.

Generally, the optimum value of the capacity of a storage device changes due to advances in integrated circuit technology, and there are cases where the capacity of the storage device and the capacity of the junctor (multiplexing number), etc. cannot be matched.

The fourth embodiment makes it possible to match the capacity of the storage device with the capacity of the junctor. For example, the junctor side highway is accessed sequentially, and the number of blocks of the storage device is set to 1/N of the number of junctor highways. In this case, in other words, when the number of blocks is less than the number of junctor highways, a decoder circuit that expands one highway into N highways is installed on the output side of the primary switch, and N highways are installed on the input side of the secondary switch. A multiplexer circuit for multiplexing highways into one highway is provided, and a junctor is configured between the decoder circuit and the multiplexer circuit.

According to this embodiment, it is possible to effectively utilize a storage device having a storage capacity greater than the junctor capacity.

Further, although this embodiment is a case in which sequential access is performed on the junctor side, the same effect can be obtained in connection with a transmission terminal equipment etc. even when sequential access is performed on the ingress/egress highway side.

The fifth embodiment is another embodiment that makes it possible to match the capacity of the storage device and the capacity of the junctor. As shown, N groups of primary switch latch circuits L1n are provided, the read pulse Rp is divided into N systems by a decoder DEC, and a multiplexer MPX is used on the write side of the secondary switch.

In this case, the operating phase of the junctor highway is dispersed into N phases, but if it is necessary to have a unified phase, a latch circuit that operates with unified timing is inserted on the output side of the primary switch (i.e., the latch circuit L is configured as a double buffer). ).

According to this embodiment, the latch circuit used for reading from the storage device can be provided with a function of matching the capacity of the storage device and the capacity of the junctor, etc., and the circuit scale can be reduced.

It goes without saying that the same effect can be obtained even if sequential access is performed on the entrance/exit highway side.

The sixth embodiment is for the case opposite to the fourth embodiment, that is, the number of storage device blocks is on the sequential access side, for example, N' times the number of junctor highways, and is on the output side of the primary switch. A multiplexer circuit is provided at the input side of the secondary switch, and a decoder circuit is provided at the input side of the secondary switch.

According to this embodiment, it is possible to configure a time-division communication path system in which the capacity of the sequential access side, for example, the junctor side, is larger than the capacity of the storage device.

Note that, similarly to the fourth embodiment, it is also possible to provide sequential access on the ingress/egress highway side.

For time-division communication highways, a serial transmission system is often used to simplify the transmission circuit.

On the other hand, storage devices in time-division communication paths are often parallel-converted for each communication channel in order to reduce the operating speed.

Therefore, conventionally, a serial-to-parallel converter and a parallel-to-serial converter were provided at the connection point between the highway and the storage device.

The seventh embodiment has the above-mentioned serial-parallel conversion and parallel-serial conversion functions, and as explained in detail in the first embodiment, the operating cycle of the latch circuit on the sequential access side is the same as that on the random access side. Since the ratio is 1/n and there is a margin in operating speed, a known shift register having a parallel input/serial output function or a serial input/parallel output function is used in place of the latch circuit.

In addition to the latch function, this shift register can realize parallel → serial conversion or serial → parallel conversion functions, and can be used at the junctor part (when the junctor side is sequential access) or the transmission line side (when the transmission line side is sequential access). , when a serial/parallel conversion function is required, the above-mentioned function can be realized without increasing the number of parts.

The serial input/parallel output or parallel input/serial output conversion function using the shift register of this embodiment can be applied to various time division calls including the one-stage time switch configuration shown in the first and second embodiments. It can also be applied to time switches in road systems.

Furthermore, the present invention can be applied to a configuration that is a combination of a conventional time switch and a space switch; for example, it can also be applied to a configuration that includes a space switch in the junctor portion of the third embodiment. It is something that can be done.

In the above explanation, the holding memory HM of the primary switch and the holding memory HM of the secondary switch can be shared, and the information line to the decoder DEC is connected to the holding memory HM.
Although an example is shown in which the decoder DEC is directly connected to the decoder DEC after passing through the selector SEL, the present invention can be applied regardless of the configuration method of the holding memory HM.

As explained above, according to the first invention (first and second embodiments) showing the basic part of the present invention, the storage device constituting the T switch is divided into a plurality of blocks, and the sequential access side Since the plurality of -j locks are accessed in parallel, there is no need for multiplexing or separating circuits on the sequential access side, and the circuit can be constructed economically.Also, since idle timing can be obtained on the sequential access side, this can be used in conjunction with other There is an advantage that the access timing can be allocated to, for example, maintenance timing.

According to the second invention, the function of parallel to series exchange or series to parallel conversion can be easily realized together with the latch function, and there is an advantage that the configuration of the connection point between the storage device and the highway can be simplified. be.

In addition to the advantages of the first invention, the third invention (third embodiment) has the advantage that, in the case of configuring a T2-stage switch with a simple control algorithm, it is possible to
There is an advantage that a junctor can be constructed between the secondary switch and the secondary switch.

Further, the fourth invention (fourth embodiment) provides that when a storage device having a storage capacity greater than the capacity of a sequential access highway, for example, a junctor highway, is used in a T2-stage switch configuration, the storage device can be effectively used. There are advantages available to you.

Furthermore, the fifth invention (fifth embodiment) has the advantage that matching between the junctor capacitance and the storage device capacitance can be realized with a small circuit scale by using a latch circuit number.

Further, the sixth invention (sixth embodiment) has the advantage that it is possible to easily configure a time division communication path system in which the capacity of the junctor is larger than the capacity of the storage device.

In addition to the effects of the third invention, the seventh invention (seventh embodiment) can easily realize a series-to-parallel or parallel-to-serial conversion function at the connection point between the highway and the storage device. There are advantages.

Furthermore, the present invention has the above-mentioned advantages even when applied to time-division channel systems including space switches, and is effective in improving time switches in various time-division channel systems.

[Brief Description of the Drawings] Fig. 1 is an explanatory diagram of an embodiment showing the basic part of the present invention, Fig. 2 is an explanatory diagram of an embodiment showing the basic part of the present invention;
The figures are explanatory diagrams of the operation of FIG. 1, and FIGS. 3, 4, and 5 are explanatory diagrams of other embodiments of the present invention. M1~n...Storage device block, Di...
...M1~n data input terminal, D0...M1
-n data output terminals, Add...M1-n address input terminals, WE...M1-n write enable terminals, BS...M1-n blocks・Select terminal, I7IwL1...Input highway, HWJO1~n...Output highway,
OR1~n...OR gate, R/W...
・Read/write control signal, SQ...Sequential address, RN...Random address, L1
~n...Latch circuit, Rp...Read pulse, WEp...Write pulse, 1MV...
...Inversion circuit.

Claims (1)

[Scope of Claims] 1. A storage device that temporarily stores call information during an exchange operation is divided into a plurality of blocks, and a predetermined block among the plurality of blocks is accessed at one access timing on the random access side to the storage device. , and the plurality of blocks are accessed in parallel at one access timing on the sequential access side to write and read the call information. 2. A storage device that temporarily stores call information during an exchange operation is divided into a plurality of blocks, and a predetermined block among the plurality of blocks is accessed at one access timing of a random access side to the storage device, The sequential access side accesses the plurality of blocks in parallel at one access timing to write and read the call information, and the sequential access side performs serial input/parallel output or parallel input/serial output. A time division communication path system characterized by being equipped with a shift register having functions. 3. In a time-division communication path consisting of two stages of time switches, the storage device that temporarily stores call information during switching operations is divided into multiple blocks, and access to either the transmission path side highway or the junker side highway is restricted. Accessing a predetermined block among the plurality of blocks at one access timing as random access, accessing the plurality of blocks in parallel at one access timing as the other access, and dividing into the plurality of blocks. A time-division communication path system characterized by making the number correspond to the number of highways on the sequential access side. 4. In a time-division communication path consisting of two stages of time switches, the storage device that temporarily stores call information during switching operations is divided into multiple blocks, and access to either the transmission path side highway or the junker side highway is restricted. A predetermined block among the plurality of blocks is accessed at one access timing as a random access, and the plurality of blocks are accessed in parallel at one access timing as an independent access, and a plurality of blocks in the storage device are accessed in parallel at one access timing. The number of divisions into blocks is set to 1/integer (N) of the number of highways on the sequential access side, and the reading side by sequential access is the integer (N) =
A time-division call system characterized in that F= highways are expanded by a decoder, and the writing side by sequential access multiplexes the integer number (N) of highways into one highway by a multiplexer circuit. 5. In a time-division communication path consisting of two stages of time switches, the storage device that temporarily stores call information during switching operations is divided into multiple blocks, and access to either the transmission path side highway or the junker side highway is restricted. A predetermined block among the plurality of blocks is accessed at one access timing as a random access, and the plurality of blocks are accessed in parallel at one access timing as the other access is a sequential access. The number of divisions is set to 1/integer N of the number of highways on the sequential access side, and the reading side by sequential access has latch circuits of the integer N groups, and the read pulse on the reading side is divided into the integer systems. The time-division communication channel system is characterized in that the integer N groups of highways are made to correspond to the latch circuits of the integer N groups, and the write side by sequential access multiplexes the integer N highways into one by a multiplexer circuit. 6. In a time-division communication path consisting of two stages of time switches, the storage device that temporarily stores call information during switching operations is divided into multiple blocks, and access to either the transmission path side highway or the junctor side highway is restricted. A predetermined block among the plurality of blocks is accessed at one access timing as a random access, and the plurality of blocks are accessed in parallel at one access timing as the other access, and the plurality of blocks of the storage device are accessed in parallel at one access timing. The number of divisions into the sequential access highways is set as an integer (N') times the number of highways on the sequential access side, and the outputs of the memory device on the reading side by sequential access are multiplexed by a multiplexer circuit into one highway, and the sequential access A time-division communication channel system is characterized in that the writing side expands one highway into the integer (N') numbers using a decoder. 7 In a time-division communication path consisting of two stages of time switches, the storage device that temporarily stores call information during switching operations is divided into multiple blocks, and access to either the transmission path side highway or the junker side highway is restricted. Accessing a predetermined block among the plurality of blocks at one access timing as random access, accessing the plurality of blocks in parallel at one access timing as the other access, and dividing into the plurality of blocks. A time division communication channel system, characterized in that the number of highways corresponds to the number of highways on the sequential access side, and the sequential access side is equipped with a shift register having functions of serial input and parallel output or parallel input and serial output. 8. The time division communication path system according to claim 3, 4, 5, 6, or 7, wherein the junk section includes a space switch stage.