JPS588589B2 - SouhoudenkaikoukaTransistorOyuusuruHandoutaiSouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary semiconductor device having a vertical field effect transistor.

In general, a vertical field effect transistor can have a shorter channel length and an increased number of gates than a lateral field effect transistor, so the effective channel width can be made much wider than that of a lateral field effect transistor. Can be done.

Therefore, this type of vertical field effect transistor is expected to be used as a power device because of its ability to reduce on-resistance, its temperature characteristics, and its resistance to secondary breakdown.

In addition, vertical field effect transistors have triode characteristics,
Due to its good linearity when used as an amplifier, it is also considered important for audio applications.

When incorporating such a vertical field effect transistor into a semiconductor integrated circuit, there is a method that has a structure that can be formed together with other circuit elements and that does not complicate the manufacturing process of the integrated circuit due to the creation of the vertical field effect transistor. need to be adopted.

Therefore, when building a vertical field effect transistor in a semiconductor integrated circuit, it is virtually impossible to apply the structure of a single element vertical field effect transistor as is.

It is an object of the invention to provide a complementary vertical field effect transistor whose structure allows it to be fabricated simultaneously with other circuit elements, in particular with bipolar transistors.

Another object of the present invention is to provide a method for manufacturing a vertical field effect transistor, which can manufacture a vertical field effect transistor with almost no modification to the process of manufacturing a bipolar transistor.

According to the present invention, a semiconductor substrate of one conductivity type, first and second regions containing a high concentration of impurities of a conductivity type opposite to that of the substrate in the form of a surface region of the semiconductor substrate, and formed on the substrate. an epitaxial layer having the same conductivity type as the first and second regions; a separation region formed to separate the epitaxial layers on the first and second regions of the epitaxial layer from each other; a third region forming a pn junction with the separated epitaxial layer by an isolation region and disposed in contact with the first high concentration impurity region; and the separated epitaxial layer on the second region. a fourth region provided to form a pn junction with the epitaxial layer; and a fifth region disposed in a relationship to form a pn junction with the fourth region; The fourth region has at least one hole at the bottom of each region, and has a structure in which the substrate and the third region and the epitaxial layer and the fifth region are respectively connected through the hole. The epitaxial layer including the first region, the third region and the semiconductor substrate constitute a first vertical field effect transistor, and the epitaxial layer including the second region, the fourth region and the fifth region constitute a first vertical field effect transistor. A semiconductor device having a complementary field effect transistor characterized in that the second vertical field effect transistor is configured by the first and second regions is obtained.

According to the present invention, the third and fourth regions are formed simultaneously when forming the insulation isolation region of the bipolar transistor, and
In addition to the second area provided at the bottom, the fourth area is also
A complementary vertical field effect transistor having a structure in contact with the region is obtained.

The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention, and here, as an example, a complementary vertical field effect transistor (
(hereinafter abbreviated as FET).

First, regions 20 and 30 are formed by n+ diffusion in a p-type silicon substrate 10 having a high specific resistance of about 5 to 8 Ω·cm.

This step is performed simultaneously with the formation of the buried layer of the bipolar transistor.

Of these regions 20 and 30, region 20 becomes the gate portion of the p-channel FET, and region 30 becomes the drain region (source region) of the n-channel FET.

For P-channel FETs, the semiconductor substrate 10 itself serves as the drain region.

Further, as shown in the figure, the region 20 is branched at its bottom, and this region 20 forms at least one hole at the bottom.

Next, the n+ regions 20 and 30 are formed by diffusion.
N-type silicon is grown on a type silicon substrate 10, and an epitaxial layer 40 is provided.

It is necessary that the n-type epitaxial layer 40 has a resistivity comparable to that of the p-type silicon substrate 10.

After forming the epitaxial layer 40, p-type impurities are diffused to form the isolation region 50 and the source region 60 of the p-channel FET.
and the gate region 70 of the n-channel FET are formed at the same time.

This step is also performed simultaneously with the formation of the isolation region of the bipolar transistor.

Thereby, the isolation region 50 is connected to the p-type silicon substrate 10, and the source region 60 of the p-channel FET is connected to the p-type silicon substrate 10.
The gate region 70 of the n-channel FET is connected to the resistance regions 20 and 30 buried in the p-type silicon substrate 10, respectively.

At this time, the gate region 70 of the n-channel FET is n+
Similar to the region 20, it is diffused so as to branch at its tip, that is, to enclose a part of the epitaxial layer 40 inside.

On the other hand, the source region 60 of the p-channel FET is provided so as to be connected to the p-type silicon substrate 10 at a part of the bottom.

Furthermore, inside the gate region 70 of the n-channel FET,
At the same time as the emitter region of the bipolar transistor, the source region 80 of the n-channel FET is formed.

In this case, the source region 80 of the n-channel FET is connected to the epitaxial layer 40 at a portion of its bottom.

Through the process described above, a p-channel FET and an n-channel FET can be fabricated at the same time as a bipolar transistor without changing the process of fabricating the bipolar transistor.

Among the regions formed by the above-described steps, the gate width of the n+ region 20 forming the gate region of the p-channel FET must be made sufficiently narrow.

Therefore, the pattern spacing must be determined by taking into account the lateral spread so that a predetermined gate width can be obtained despite the effects of subsequent epitaxial growth, isolation diffusion, and base diffusion of bipolar transistors. .

This also applies to the gate region 70 of the n-channel FET, and the spacing between the gate patterns needs to be determined experimentally, also taking subsequent steps into consideration.

Note that in order to reduce the area of the element, it is preferable to make the width of the gate pattern very narrow, such as several microns.

Further, regarding the source region 60 of a p-channel FET, if this region is too shallow, a channel will not be formed;
On the other hand, if it is too deep, the gate width will become wide.

Therefore, it is necessary to accurately control the temperature and time of separation and diffusion.

This hump is also a problem for the source region 80 of the n-channel FET.

In the embodiment shown in FIG. 1, the n-channel FET north region 80 is formed at the same time as the emitter region of the bipolar transistor, so the impurity concentration in the source region 80 is high.

On the other hand, a gate region 70 forming a junction with a source region 80
Since the p-type impurity concentration is also relatively high, n-channel FE
The breakdown voltage between the source and gate of T is only about 6V.

Therefore, if this level of breakdown voltage is insufficient, n
A low concentration of n is separately applied to the source region 80 of the channel FET.
Type diffusion may also be performed.

Note that this n-type region can also be formed at the same time as the collector electrode portion provided to lower the collector series resistance of the bipolar transistor.

FIG. 2 is a cross-sectional view showing another embodiment of the invention, in which only an n-channel FET is shown.

In this embodiment, the gate region 90 of the n-channel FET is formed at the same time as the base region of the bipolar transistor, and its bottom is branched, but not connected to the lower n+ region 30).

This method has the advantage that the depth of the gate region 90 is shallower than in FIG. 1, and the gate width can be easily controlled.

As described above, according to the present invention, for example, a complementary vertical field effect transistor can be manufactured without increasing the number of steps for manufacturing a bipolar transistor.

Therefore, it is possible to easily obtain a semiconductor integrated circuit equipped with bipolar transistors and complementary vertical field effect transistors, and the functionality of the semiconductor linear IC can be greatly improved.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing one embodiment of the invention, and FIG. 2 is a sectional view showing another embodiment of the invention. 10: p-type semiconductor substrate, 20: n+ buried region (gate region of p-channel FET), 30: n+ buried region (drain or 'north region of n-channel FET), 40:
n-type epitaxial layer, 50: insulation isolation region, 60: p
Channel FET source or drain region, 70:n
Gate region of channel FET, 80:n channel F
Source or train region of ET, 90: Gate region of n-channel FET formed simultaneously with base diffusion layer.

Claims (1)

[Claims] 1 comprising a semiconductor substrate of one conductivity type, first and second buried regions of opposite conductivity type provided on the semiconductor substrate, and an epitaxial layer of opposite conductivity type provided on the semiconductor substrate, The first buried region extends in the semiconductor substrate in a branched manner, and a first impurity region of one conductivity type provided in the epitaxial layer on the first buried region is located on one bottom surface of the first buried region. The first impurity region, the first buried region, and the semiconductor substrate form a one-channel field effect transistor; A second impurity region of one conductivity type extends in a branched manner in a portion of the epitaxial layer above the region, and a third impurity region of the opposite conductivity type extends within the second impurity region. the second
A semiconductor device having a complementary field effect transistor, characterized in that a reverse channel field effect transistor is formed by the impurity region, the second buried region, and the third impurity region.