JPS588773B2 - digital tuner - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital tuner in which switching of the sweep frequency is controlled by a simple circuit.

FIG. 1 shows a conventional digital tuner.

In FIG. 1, a sweep pulse output from a pulse generator 1 is supplied to an up-down counter 3 via a gate 2 which is opened in accordance with a sweep command.

The counter 3 starts counting by a sweep pulse, and supplies its output, for example, an 8-bit output, to the PLL section 4 and the display 5.

Then, the PLL section 4 automatically sweeps the receiving frequency, and the display 5
to display the received frequency.

On the other hand, the above 8-bit output is also supplied to detection circuits 6 and 7 that detect the upper and lower limits of the frequency band, respectively. In the case of up-counting, the upper limit detection circuit 6 detects the upper limit frequency of the reception band, and The lower limit frequency data is supplied to the preset input of the counter 3 via the switch circuit 8.

Further, in the case of down-counting, the lower limit detection circuit 7 detects the lower limit frequency of the receiving band, and supplies the upper limit frequency data to the preset input of the counter 3 via the switch circuit 8.

Note that 9 is a control circuit that switches the counter 3 and the switch circuit 8 according to up-counting and down-counting.

In this way, Japan's FM reception frequency band (approximately 7
For example, when up-counting, 7 6. 0 MHz to 9 0. 0MHz
The upper limit detection circuit 6 detects when the frequency reaches 90.0 MHz and supplies the output to the preset input of the counter 3. 0
Switched from MHz to 76.0MHz, then back to 90.0
One can start sweeping towards MHz.

The operation can be similarly reduced in the case of a down count.

However, when configured in this way, it is necessary to provide detection circuits 6 and 7 at both the upper and lower limits when sweeping the received frequency higher and lower, respectively. In order to detect the output corresponding to the numerical values .0 MHz and 90.0 MHz, it is necessary to detect changes in most bits of the 8-bit output, which causes a problem that the circuit configuration becomes complicated.

Furthermore, in order to directly detect the upper and lower limits of the reception frequency band and perform sweep switching, there is a restriction that a counter with a preset input must be used.

The present invention provides a digital tuner that solves these conventional problems.

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 2, 10 and 11 are pulse generators that output low frequency sweep pulses and high frequency sweep pulses, 12 is a switch circuit that switches these pulses, 13 is a gate circuit that is opened by a sweep command, and 14 15.16 is an up-down counter, 15.16 is a PLL unit and display driven by the output thereof, 17 is a detection circuit that detects when the count number of the counter 14 is outside a preset range, and 18 is a detection circuit of the counter 14. This is a control circuit that switches between up-counting and down-counting.

Here, for convenience of explanation, it is assumed that the counter 14 counts 1 for each receiving frequency of 100 KHz, the 10's digit is a binary number, the 1's digit is a BCD, and when it counts up to 160 counts, it returns to an O count.

That is, 76. of the FM broadcast frequency band. 0MHz
From 9 0. 14MHz up to 0 MHz 100K
It is assumed that 140 counts are made for each Hz, and when the count exceeds 160, it overflows and returns to O count.

In the above configuration, first 76. Consider the case where the frequency is sequentially swept from 0 MHz to higher frequencies.

In this case, the signal from the suppressing circuit 18 causes the counter 1 to
4 is set to an up-count state, and when the gate 13 is opened by a sweep command, a low frequency sweep pulse is supplied from the pulse generator 10.

Therefore, the counter 14 is 76. Count 1 count for every 100 KHz from 0 MHz,
When swept to 89.9 MHz, it reaches 139 counts.

At the moment when the 140th count is reached, the detection circuit 17 detects a change in the output of the counter 14, uses the output to switch the switch circuit 12, and supplies high frequency pulses from the pulse generator 11 to the counter 14.

Therefore, the counter counts from 140 to 159 in an instant, and returns to O count at the moment it reaches the 160th count.

When the count returns to 0, the output of the counter 14 also falls within the range of 140 counts or less, so the detection circuit 17
The output of the switch circuit 12 causes the pulse generator 10 to switch again.
and the counter 14 is switched back to 76. 0M
Hz to 90. Start counting towards 0 MHz.

Here, detection of the range string can be realized by only detecting the L-order 3 bits, as shown in FIG.

On the other hand, when counting sequentially from 90.0 MHz to lower frequencies, only the counter 14 is set to a down-counting state, and the other operations are the same as in the case of up-counting described above.

As described above, according to the present invention, it is possible to switch the sweep frequency simply by detecting whether the count number of the counter exceeds a preset range. The circuit configuration can be simplified compared to a system that detects both separately.

In addition, in the conventional case, it is necessary to detect most of the bits of the output such as 8 bits or 4 bits in order to detect that the upper limit or lower limit has been reached, but according to the present invention, the It is only necessary to detect the bit indicating that the specified range has been exceeded, and the circuit configuration can be simplified in this sense as well, since the counter can be configured with a counter without a preset input.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional digital tuner.
FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is an explanatory diagram of its operation. 10.11... Pulse generator, 12... Switch circuit,
13...Gate circuit, 14...Counter, 15...PL
L section, 16...display device, 17...detection circuit, 18...control circuit.

Claims (1)

[Claims] 1. A pulse generator that generates two types of sweep pulses, low frequency and high frequency, a counter driven by this pulse generator, a PLL section that sweeps the reception frequency using the output of this counter, and a a detection circuit that uses the second part to detect that the count number of the counter has reached a preset range string; and a switching circuit that switches between the two types of sweep pulses based on the output of this detection circuit; When the output of the counter is within a preset range, the counter is driven with a low frequency sweep pulse, and when it is at the edge of the preset range, it is driven with a high frequency sweep pulse, and the counter is driven with a high frequency sweep pulse when the output is within the preset range. A digital tuner characterized in that the digital tuner is configured to cause a counter to count at a high speed until it overflows outside a preset range, reset the counter, and start counting again at a low speed from the end of the preset range.