JPS589446B2 - Data bus noise suppression method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise suppression scheme on a data bus.

Data buses are widely used in data processing systems as a common data transmission path between multiple units.

The signal line group constituting the data bus is divided into data lines for transmitting data itself and tag lines for transmitting various control signals when exchanging data between units.

In recent years, data processing systems have been required to perform increasingly large amounts of processing and high-speed processing. When increasing the speed of the above signals, noise on the data bus becomes a problem.

Tag lines are easily affected by noise caused by changes in data on the data line, but if the control signal is disturbed by noise mixed into the tag line, the control of data transmission will be disrupted, so the effect is serious. .

To deal with this, conventionally the data bus was divided into sections of appropriate length and reconnected via a bus repeater, but due to the delay in the operation of the bus repeater, the data transmission The disadvantage is that the speed is slow and high speed is sacrificed.

There are two types of noise that enter the tag line: one whose polarity changes the active level signal of tag line 1 to a non-active level, and another whose polarity changes a non-active level signal to an active level. The influence is greater on noise that changes an active level signal to a non-active level.

This is because even if the tag line active signal generated according to the normal sequence of data transfer becomes non-active due to noise, the receiving side cannot distinguish the signal from one that has finished normally and cannot respond to it. This is because there is a risk that an abnormal sequence may occur.

On the other hand, when the non-active signal on the tag line becomes active due to noise, regardless of the normal data transfer sequence, this can be identified relatively easily by checking the sequence, so malfunctions can be avoided. It is possible.

An object of the present invention is to provide a method for suppressing noise mixed into active level tag lines without sacrificing data transmission speed.

In the present invention, a tag line to which an active level signal is applied by a drive circuit is forced to reach an active level output point with low impedance over the entire line for a time that does not exceed the duration of the regular signal. It was designed to connect.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a conceptual configuration diagram of an example of a data processing system to which the present invention is applied.

In FIG. 1, 1 is a processor, 21 to 24 are main memory units, and 3 is a data bus.

Processor 1 and main memory units 21-24 are connected by data bus 3.

The data bus 3 consists of a data line 31 and a tag line 32.

The data line 31 is for transmitting data exchanged between the processor 1 and the main memory units 21 to 24, and is composed of, for example, 20 signal lines corresponding to the number of bits of data.

The tag lines are for transmitting control signals that order the transmission and reception of data, and four signal lines are illustrated here assuming data transmission using an asynchronous confirmation method.

Low-level active signals are transmitted through these signal lines.

The drive circuit is an open collector type circuit.

Data transmission via the data bus 3 is performed as follows.

Explanatory diagrams of the operation are shown in FIGS. 2 and 3.

In Figure 2, processor 1 is connected to main memory unit 2i.
When data is read from (l=i to 4), FIG. 3 shows a case where the processor 1 writes data to the main memory unit 21.

In the case of data reading in FIG. 2, the processor 1 sends address data specifying a read address to the data line 31, and also sends a memory activation command to the first tag line MSELO.

The main address whose address matches the address data
When the memory unit, for example 21, receives the activation command, it sends a response signal to the second tag line MRSP.

When processor 1 receives this response signal, it sends a data output command to third tag MDATO.

When the main memory unit 21 receives this command, it sends the data read from the address designated five earlier to the data line 31, and also sends a data input signal to the fourth tag line MDATI.

When processor 1 receives this data input signal, it reads the data on data line 31 and erases the data output command on tag line MDATO.

Main memory unit 21 detects that the command on tag line MDATO disappears and erases the signal on tag line MDATI.

Processor 1 detects that this signal disappears and erases the memory activation command on tag line MSELO.

Main memory unit 21 detects that this command has disappeared and erases the response signal on tag line MRSP.

This completes the read operation of one word of data.

In the case of data writing as shown in FIG. 3, first, the processor 1 sends address data specifying a write address and a memory activation command.

When there is a response from the main memory unit 21, the processor 1 sends write data onto the data line 31 and sends a data output command onto the tag line MDATO.

When main memory unit 23 receives this command, it writes the data on data line 31 to the previously specified address, and then sends a data input signal to tag line MDATI.

When this signal is detected by the processor 1, the data output command is deleted, and accordingly, the remaining signals and commands are deleted as in the case of FIG.

When such an operation is performed, on the data line 31,
The rise and fall of address data, read data, and write data are performed.

Since there are many data lines 31, the rising edge of the signal there,
When falling occurs, cross talk to tag line 32 occurs.
Noise and common potential fluctuations occur.

This can cause a lot of noise to the tag line which is in the low level active state.

However, a circuit as shown in FIG. 4 is provided at the tag line ends of the main memory units 21 to 24 to suppress noise.

That is, in the main memory unit 21 of FIG. 4, a low-level clamp circuit CLP consisting of a NAND gate G1 and a simple circuit MM is connected to the input side of the receiving circuit H for the tag line MSELO. , tag line MRS
A low-level clamp circuit CLP2 consisting of an inverter 1, a NAND gate G2, and a monostable circuit MM2 is provided on the output side of the 1-drive circuit D for P.

Similar low-level clamp circuits are provided for the receiving circuits and driving circuits for other tag lines (Figure omitted).

The other main memory units 22 to 24 have similar configurations.

The low level clamp circuit CLP operates as follows.

That is, when the signal level of the tag line MSELO becomes "L", the output of the receiving circuit R becomes "H", so that the "H" manual signal is sent to the NAND gate G1, one directly and the other simply. They are respectively given via the stabilizing circuit MM1.

Therefore, the output signal of the NAND gate G1 remains "L" as long as the "H" output signal of the monostable circuit continues.

That is, the input side of the receiving circuit R is clamped to a low level for a set time T1 of the monostable circuit MM1 after the arrival of a low-level active input signal.

The low level clamp circuit CLP2 provided on the output side of the drive circuit D also operates in a similar manner when the signal on the tag line MRSP becomes low level.

The tag line signal is transmitted to other main memory units 22 to 22.
24, similar low-level clamping of the tag lines is performed in all main memory units 21-24.

Therefore, when a low level active signal is applied to a certain tag line, all lines of that tag line are clamped at low level.

When such low level clamping is performed,
Since the entire tag line is connected to the common point with low impedance, even if noise is added to the tag line, the voltage level will hardly be affected.

The duration of the low-level clamp is determined by the monostable circuit of the low-level clamp circuit to be shorter than the duration of the control signal on the tag line and to include the data change period on the data line 31 during that time. It will be done.

An example of this for the tag lines MSELO and MRSP is T1 and T2 in FIGS. 2 and 3.

The tag lines MDATO and MDATI are similarly defined.

In this way, the low-level active control signal on the tag line will not be affected by noise caused by data changes on the data line 31, so stable operation can be achieved without sacrificing high speed. .

Note that depending on its polarity, noise may lower the level of the high-level non-active signal on the tag line.

If such noise causes the non-active signal to temporarily drop below the threshold level of the logic circuit, the active level will become fixed due to the action of the low-level clamp circuit, causing a problem.

However, such inconveniences can be made less likely to occur by setting the threshold level sufficiently low, and even if it happens to be clamped low, the signal on the tag line will not follow the normal sequence. Since the abnormality can be easily detected by becoming active without any error, it is possible to appropriately prevent malfunctions.

The above is an example in which the present invention is applied to data transmission between a processor and a group of main memory units, but the present invention is not limited to such an example, but can be applied to general data transmission using a data bus.

Furthermore, the duration of the low-level clamp may be determined by monitoring other tag line signals and using appropriate logic, instead of using the monostable circuit.

In addition, a low-level clamp circuit was provided on each unit side, so that when a unit was connected to a data bus, the low-level clamp circuit was automatically connected to that part of the data bus. The clamp circuit may be separate from the unit group and connected to an appropriate location on the data bus.

Furthermore, the idea of the present invention is not limited to data buses that transmit low-level active signals, but can also be applied to data buses that transmit high-level active signals.

As described above, in the present invention, a tag line to which an active level signal is applied by a drive circuit is forcibly set to an active level at low impedance for a time that does not exceed the duration of the regular signal over the entire tag line. It was made to connect to the potential point of .

Therefore, noise mixed into the active level tag line can be suppressed without sacrificing the data transmission speed.

[Brief explanation of drawings]

FIG. 1 is a conceptual configuration diagram of an application example of the present invention, FIGS. 2 and 3 are explanatory diagrams of the operation of the device in FIG. 1, and FIG. 4 is a detailed diagram of a part of the device in FIG. 1. . DESCRIPTION OF SYMBOLS 1... Processor, 21-24... Main memory unit, 3... Data bus, 31... Data line, 32
... Tag line, R ... Receiving circuit, D ... Drive circuit, I ...
Inverter, Gl, G2... NAND gate, MM1,
MM2...monostable circuit.

Claims (1)

[Claims] 1 In a data bus consisting of data lines and tag lines,
When an active level signal is applied to the tag line,
The tag line is forced across substantially the entire length of the line for a period that is within the duration of the normal signal agtainer level on the tag line and that includes the data switching period on the data line within that period. Noise suppression method that connects to the active level potential point with low impedance.