JPS589513B2 - Semiconductor memory selection circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a semiconductor memory selection circuit.

Conventional semiconductor memory selection circuits include static type and dynamic type circuits.The static type is used for low-speed writing and needs to be maintained at a constant level for a long time, while the static type is used for high-speed reading. Generally, a dynamic type is used.

However, it is possible to operate both static and dynamic types by switching dimming, etc., but the former has a slow read speed, and the latter consumes a lot of power when writing, and the output remains constant for a long time. There is a drawback that it cannot be done.

Therefore, there is a need for a semiconductor memory selection circuit that is high-speed when reading and low-power when writing.

An object of the present invention is to provide a semiconductor memory selection circuit capable of high-speed selection operation.

A semiconductor memory selection circuit according to the present invention includes a decoder circuit;
a first transistor for a buffer drive whose drain is supplied with a signal and whose source is supplied with a signal to be selected by the output signal of the decoding circuit; an output of the decoding circuit; a second transistor that is provided to form an electrical path with the gate of the first transistor and to which a first control signal energized during readout is applied; and a dynamic type decoder circuit. a load transistor that is connected in parallel to the load and is turned on by a second control signal that is energized during writing with a conduction resistance that is thicker than the dynamic load; and a connection between the output of the decoder circuit and the line to be selected. and a third transistor connected between them and having a gate applied with the second control signal.

According to the present invention, the selection signal from the decoder applied to the gate of the first transistor by the second transistor is increased in value by the so-called boot effect due to the gate-drain-source capacitance of the second transistor, and this increase is caused by the so-called boot effect. Since the second transistor is saturated at this time, the selection signal having a high value does not leak to the decoder side.

The line to be selected for this purpose ensures that the signal applied to the drain of the first transistor is applied at the same level.

Therefore, a selection circuit capable of low-power writing and high-speed reading is obtained.

Furthermore, in the present invention, the decoder circuit is provided with a load that operates during writing in parallel to the dynamic load, and the line to be selected by the fourth transistor during writing is directly connected to the output of the decoder circuit. The selection level is maintained for a relatively long period of time.

Thereby, selection characteristics optimized for both reading and writing can also be realized.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

Note that the transistor will be explained as an N-channel MOS transistor.

FIG. 1 shows a conventionally known static type semiconductor memory selection circuit.

This circuit consists of transistors Q1 to Q whose source terminals are grounded.
3 are commonly connected, and these drain terminals are connected to the source terminal of transistor Q4, and Q1 to Q3 are connected in common.
This is the most basic decoder circuit 1, in which address signals A1 to A3 are connected to each gate terminal of Q4, and power supply VDD and timing φ1 are connected to the drain terminal and gate terminal of Q4, respectively.The output of this circuit is as follows. Connected to address line AL1 coupled to memory cells.

In this example, since there are three address signals, the address 23-8 is selected.

Therefore, although not shown in the figure, there are eight decoder circuits 1, and these decoder circuits are used to select eight address lines respectively coupled to memory cells M arranged in eight rows.

When the address is 2N, the number of address signals required is N, and therefore the number of transistors connected in parallel in each decoder circuit is N.

The operation of FIG. 1 will be explained with reference to the timing diagram of FIG. 2.

In FIG. 2, when φ1 goes high at timing t1, some of the address signals Ai (hereinafter referred to collectively as A1 to A3) go high.

In the figure, the broken line portion where Ai continues to remain at a low level means that all of the address signals A1 to A3 continue to remain at a low level.

When address signal Ai is low level, address line AL1
is at a high level, and when the address signal Ai is at a high level, the address line AL1 is at a low level.

Thus, the address where all of the address signals A1 to A3 are at low level is the selected address, and in the decoder circuit of the selected address, AL1 is at high level as shown by the broken line.

In non-selected decoder circuits, AL1 is at a low level as shown by the solid line.

In the static decoder circuit that operates at such timing, the unselected circuit operates at timing t1.
Thereafter, since the transistor Q4 is on and at least one of the transistors Q1 to Q3 is on, a current flows from the power supply VDD to the ground through the transistors Q4 and Q1 to Q3.

Therefore, the power consumption of the unselected decoder circuit becomes very large, so the transistor Q4 is made to have a high resistance (R).

) to minimize power consumption.

The rise time of AL1 at this time is approximately 2.3 CLR, which corresponds to t2-t1 in FIG.

This state type circuit is often used when it is necessary to keep the address line AL at a constant level for a long time, such as during writing.

Further, although the circuit shown in FIG. 1 is normally used as a static type decoder circuit, it will be explained with reference to the timing diagram of FIG. 3 that by changing the timing, it becomes a dynamic type decoder circuit.

In FIG. 3, when φ1 becomes high level at timing t1', address line AL1 begins to rise to high level.

At timing t2' when AL1 becomes high level, φ1 returns to low level.

When φ1 returns to low level, address signal Ai becomes high level at timing t3' (timing t4') and AL
1 begins to descend towards a lower level again.

This operation is a non-selective decoder circuit.

On the other hand, the output of the selected decoder circuit, that is, AL1, maintains a high level as shown by the dotted line in the figure due to the load capacitance C after timing t3', but as time passes, the level gradually decreases due to the discharge of the load capacitance C, and remains at the high level for a long time. Since timing φ1 and address signal Ai do not overlap in dynamic operation, transistors Q4 and Q1 are generally used for reading but not for writing.
~Since no current flows directly to the ground through Q3, power consumption can be reduced.

However, in order to quickly raise the potential of the address AL, that is, to increase the speed, the transistor Q4 is made to have a low resistance (R/), unlike the static type.

). The rise time at this time is t2' - t1' - 2.3 CLR'.

In this way, dynamic circuits are used for high-speed reading.

As described above, by changing the timing φ1, it is possible to perform the static or dynamic operation of the decoder circuit shown in FIG. When a decoder circuit designed as a dynamic type is operated in static mode, there is a drawback that power consumption increases because the resistance R' is low.

Therefore, there is a demand for a semiconductor memory selection circuit that improves this drawback, that is, a semiconductor memory selection circuit that can dynamically perform high-speed reading and statically perform low-power writing.

Embodiments of the semiconductor memory selection circuit of the present invention will be described below with reference to FIGS. 4 to 6.

FIG. 4 shows an embodiment of the selection circuit of the present invention.

The characteristic structure of the present invention resides in transistors Q5 and Q6.

That is, the output D1 of the decoder circuit 1 is set to the correct timing for reading. The source terminal of the transistor Q is connected to the gate terminal of a buffer drive transistor Q6 whose drain terminal is connected to the drive timing φ2.

Transistors Q7 and Q8 are provided for writing.

The power supply VDD and timing φ8 are connected to the drain terminal,
The source terminal of the buffer drive transistor Q6 whose gate terminal is connected to the output D1 of the decoder circuit 1 is connected to the address line AL.
Connected to 1.

In this circuit, transistors Q1 to Q4, Q5, Qa
The dynamic operation of the transistors Ql~Qs,Q? ，
Perform a static operation with Qa.

Next, the dynamic operation, which is a feature of the present invention, will be explained with reference to the timing diagram of FIG.

Read/write switching timing φ8,j at timing t1''
8 becomes low level and high level respectively, transistors Q4 and Q5 are turned on and Q?8 becomes low level and high level respectively. , Qa are turned off and φ1 begins to rise to a high level.

When φ1 becomes high level, the outputs D1 and D of the decoder circuit
At timing t3'' when D1 starts to rise to a high level and D1 becomes a high level, φ1 returns to a low level.

When φ1 returns to low level, address signal Ai starts to rise to high level at timing t4''.

Address signal Ai becomes high level (timing t5''
), DI and D2 begin to fall toward low levels again.

Drive timing φ2 starts to move from timing t6'' when it is determined whether D1 and D2 are high level or low level.

When drive timing φ2 becomes high level, it is determined whether address line AL1 is at low level or high level.

In the selection circuit of the selected address, since DI>D2 is at a high level as shown by the broken line, the address line AL also rises to a high level from timing t7''.

In the non-selected circuit, D1 is at a low level as shown by the solid line, so the address line AL1 also remains at a low level.

In this dynamic operation circuit, since the timing φ1 and the address signal Ai do not overlap, no current flows directly from the power supply VDD to the ground through the transistors Q4, Qt to Q3, so the resistance R4 of the transistor Q4 is made low resistance and the decoder circuit The rise time t3 and t2'' of the outputs D1 and D2 can be reduced.

This allows for faster reading.

As explained above, it has been found that a semiconductor memory selection circuit capable of high-speed reading can be obtained.

FIG. 6 shows another embodiment of the invention.

This circuit is shown in Fig. 5 with a putot strap capacitor CB connected between the gate terminal and the source terminal of the transistor Q6, the gate terminal connected to the timing φS, the drain terminal connected to the gate terminal of the transistor Q6, and the source terminal connected to the ground. A transistor Q is added.

Transistor Q5 and capacitor CB are transistor Q
This is for level compensation so that all the supply voltage at the drive timing φ2 at the drain terminal of Q6 goes to the source terminal of Q6 and is used as an output without effectively lowering the level.

Note that the transistor Q, rapidly discharges the charge of the capacitor CB during writing (when the timing φ, becomes high level), and D2 is floating in the figure 5. It has a function to prevent malfunction by setting it to ground potential.

The read/write operation in FIG. 6 is the same as in FIG. 5. It is clear that the drain terminal of transistor Q7 in FIGS. 5 and 6 may be connected to another power source instead of the power source VDD.

All of the above applies to N-channel MOS, but it may also apply to P-channel. In this case, the relationship between the power supply voltage, high level, and low level is negative voltage, negative potential, zero, or ground, respectively.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a conventional semiconductor memory selection circuit. 2 and 3 are timing diagrams of the static type and dynamic type operations shown in FIG. 1, respectively. 4 and 6 show embodiments of the semiconductor memory selection circuit of the present invention. FIG. 5 is a timing diagram illustrating the operations of FIGS. 4 and 6. Q1 to Q9: field effect transistor; CL: load capacitance; CB: boot-trap capacitor; M: memory cell; 1: decoder circuit.

Claims (1)

[Claims] 1. A dynamic load and a load transistor connected in parallel with the dynamic load, to which a first control signal activated during writing is applied to the gate, and whose resistance when conducting is greater than that of the dynamic load, and a drain. a first transistor for a buffer drive configured to supply a signal from the source to a line to be selected by the output of the decoding circuit; a second transistor provided between the gate of the transistor and a second transistor to which a second control signal activated during reading is applied to the gate, and the line to be selected and the output of the decoding circuit. a third transistor connected to the gate and having the first control signal applied to the gate thereof.