JPS589520B2 - storage controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage control device, and more specifically to a storage control device that eliminates interrupt wait time for error correction in a memory system that performs error correction using a plurality of steps.

In general, horizontal and vertical parity checks have been known as methods for detecting errors by adding redundant bits to stored information. As a simple improvement of the correcting code method, there is an error correction function (particularly used in small machines) by repeating read/write (inversion).

FIG. 1 shows an error detection/correction circuit mainly used in small machines.

In the figure, a request receiving circuit RC1 first receives a data request, and the address at that time is stored in an address register AR2.
Latch at.

Then, the data is read from the corresponding address of the storage device MMU3, and an error check is performed by the parity checker PC4.
If there is no error, the data is output as is.

If an error is detected in the parity checker PC5, it is recorded in the correction circuit CC5, the signal F1 is generated to latch the data, and the data inverted by the inverter I6 is transferred to the storage device M.
Write to MU3.

When this cycle ends, signal F2 is output, data is read out again, and the data is latched into data register DR7.

When this cycle ends, a signal F3 is output, and the data in the data register DR7 is further inverted by the inverter I6 and written to the memory device MMU3. At the same time, the gate of the gate circuit G8 is opened and the data is output, causing an error. Finish the correction.

During this time, data requests from others will not be accepted.

The following example briefly summarizes the above operations.

(This is an example of error correction in multiple steps, and the starting point is data with dropped bits.) However, when error correction is performed in multiple steps like this, even if there is an access from another, there is no normal error until the error correction is completed. The disadvantage is that the user has to wait for several times the access time.

The present invention has been made in view of the above drawbacks, and provides a storage control device that improves processing time by providing a plurality of sets of hardware and determining which hardware to use using a priority control circuit. The purpose is to provide.

The present invention will be explained in detail below using FIG.

FIG. 2 shows an embodiment of the storage control device according to the present invention,
This is a case where two multi-step error correction functions are provided.

In the figure, reference numerals 11 and 12 indicate interrupt request receiving circuits RCA and B from two places, 13 indicates a priority circuit PRO that determines the priority of accepted interrupt requests, and 14 and 15 indicate address registers ARA.B, respectively. ARB, 16, 17
18 is an inverter I for inverting data, 19 is a gate circuit G for sending out data after error correction, 20 is a storage device, 21. are data registers DRA and DRB, respectively.
22 is an error correction control circuit CCA.22 which controls READ/WRITE and each register for error correction. CCB, 23 is a parity checker PC.

That is, the priority circuit PRC13 is inserted into the storage control device shown in FIG.
All around 0 are divided into two sets.

The operation of the storage control device shown in FIG. 2 will be explained in detail below.

First, two request reception circuits RCA, RCB11 and 12 accept interrupts.

A priority competition is then made in the priority circuit PRC13, and among the accepted interrupt requests, one with a higher priority is selected, and the address register ARA14/
Data register DRA16, address register ARB
15/data register DRB17 and one of the correction control circuits CCA, CCB21, 22 is selected and operated.

The error correction method is the same as in the conventional system. When a parity error is detected by the parity checker PC 23, for example, if the priority is A, the correction control circuit CCA 21 operates and the address register ARA14/
The data register DRA16 is operated, the read data is latched by the signal A1, and after the data is inverted by the inverter I18, it is written to the memory device MMU20.

After this cycle is completed, the data is read out again using the signal A2 and latched into the data register DRA16.

When this cycle ends, the signal A3 is output, inverts the data latched in the data register DRA16, and opens the gate circuit 19 to send out the data, thereby completing reception and error correction.

The same operation applies to B. In addition, the address/data registers ARA, DRA14, 16 for A, and the address/data registers ARB, DRB15, 17 for B.
is controlled by the priority circuit PRC13, so the data being corrected is held, and even if a request comes while error correction is in progress, the process can proceed to error correction after processing the higher priority one. , the waiting time for correction is omitted.

As described above, according to the present invention, errors for which the memory has been occupied for a long time are quickly processed with high priority, thereby eliminating waiting time.

Therefore, the processing time is improved, and since it is a simple improvement over the ECC method, an inexpensive and effective system can be provided.

[Brief explanation of drawings]

FIG. 1 shows a conventional storage control device, and FIG. 2 shows an embodiment of the storage control device according to the present invention.

Claims (1)

[Claims] 1. A plurality of sets of request receiving circuits that accept interrupt requests from the outside, a plurality of sets of address and data registers that latch addresses and data of the requests, and a parity checker that checks data in the memory device corresponding to the addresses. and a plurality of sets of error correction control circuits that perform correction control by repeating reading and writing when an error is detected in the parity checker, and the data latched in the data register under the control of the error correction control circuit. An inverter that inverts data and writes it to a memory device, and a priority that selects which of the plurality of circuits and registers to use by determining the priority of the interrupt request accepted by the request acceptance circuit. A storage control device comprising: a control circuit.