JPS589611B2 - N Shin counter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an n-ary counter, and more particularly to an n-ary counter in which the magnitude of frequency division can be electrically easily changed.

A conventional n-ary counter can be achieved by connecting m-bit binary counters if n is 2 to the m power.
If n is not a power of 2, 2rn t< n(2
Select m that satisfies the inequality rn, provide m flip-flops, operate 0 to 2m-11 as a normal binary counter, and calculate the required number of states from 2m-1+1 to n from the remaining 2m-1 states. A method is used to extract only the

At this time, there are two known methods for extracting the required number from the remaining 2m-1 states: one is to count up to n and clear it by feedback, and the other is to skip the unnecessary number in the middle and return to the initial count value. There is.

However, as mentioned above, an n-ary counter using such a binary counter requires gates required for external feedback in addition to the binary counter itself.

Therefore, once n is set to a certain number, if it is desired to change it to another number, the wiring and gate structure must be completely changed.

In addition, when integrating this type of n-ary counter, in order to apply feedback to any bit, the output of each bit must be output as a pin outside the package, and a preset and clear signal to input the feedback output must be provided. The input terminal to be added must come out as a pin.

Therefore, as the number of n increases, an enormous number of pins is required.
This will be a major financial disadvantage when it comes to agglomeration.

Furthermore, in order to determine the connections when configuring the above-mentioned n-ary counter, it is necessary to solve equations using Boolean algebra, simplify them, and understand the possible state transitions.For example, when the power is turned on, combinations are prohibited. The counter may become locked and not work.

In order to eliminate this inconvenience, measures such as clearing the counter once every time the power is turned on are taken, but the configuration becomes complicated accordingly.

Furthermore, the above-mentioned conventional n-ary counter has n-ary during counting operation.
It is completely impossible to change history.

The present invention was made to eliminate the drawbacks of conventional n-ary counters, and when constructing an n-ary counter, there is no need to have a feedback loop due to the wiring connection and gate addition specific to each n-ary, and it is possible to simultaneously It is an object of the present invention to provide an n-ary counter that does not require outputs from each bit and input terminals to be led to the outside when setting the base-ary counter.

Furthermore, in the present invention, n can be set without complicated procedures,
Moreover, it is an object of the present invention to provide an n-adic counter that can electrically easily change n even while the counter is in operation.

By incorporating an electrically non-volatile memory into the counter, the present invention enables arbitrary
This realizes a forward counter.

The present invention will be described in detail below with reference to the drawings.

As described above, the present invention is based on providing a nonvolatile semiconductor memory capable of performing storage operations inside the counter.

A counter having a non-volatile semiconductor memory is described in detail in Japanese Patent Application No. 109005/1985, which was previously filed by the applicant, but this will be briefly explained using FIG. 1.

Figure 1 shows the basic configuration of the nonvolatile counter circuit2.
This shows the circuit configuration for one bit of the decimal bit.

(MTI) and (MT2) are p-channel MNO3 transistors, (T1) to (T7) are p-channel MOS transistors, and a total of nine elements constitute one bit.

Among the above nine elements, the active elements (T,), (T2
) is a flip-flop switching MOS transistor, and (T5) and (T6) are load MOS transistors.
In the transistor, (T7) is the stray capacitance (C1), (C2
) is a discharge MOS transistor.

In addition, (T7) means that the flip-flop is undefined, that is, MOS
It functions to turn off both transistors (T1) and (T2) and reduce charges in stray capacitances (CI) and (C2) in the same way.

MNOS transistor (MTr), (MT2
) is the switching MOS transistor (T1),
(T2) and load MOS transistor (T5)
, (To).

Still MNOS transistor (MTI), (MT
2) MOS as a switching element in parallel to each
Transistors (T3) and (T4) are provided.

Here, the load MOS transistors (T5), (T6
) are depletion type MOS transistors, and all other MOS transistors are enhancement type.

The MNOS transistor (MTt
) > (MT2) means that when a positive erase voltage (for example, +24) is applied to the gate substrate, the gate threshold voltage moves in the positive direction, and a negative write voltage (
For example, a device in which the gate threshold voltage moves in the negative direction when a voltage of −24 V is applied is used.

Also, in this figure, the signal (M) is the MNOS transistor (
MT1), (MT2) information restoration, information deletion,
Control signals for writing information, (DD), (VS
S) is a power supply voltage, and S) is a control signal for operating this nonvolatile counter circuit as a normal counter circuit.

In this circuit, when energized, the signal (M) causes the MNOS to
Transistors (MT,), (MT2) are turned off, and M, which is connected in parallel to the MNOS transistor by signal transmission, is turned off.
Turn on OS transistors (T3) and (T4).

Therefore, in this state, this counter operates as a normal MOS flip-flop.

Let us now consider the case where the contents of this flip-flop are written into the MNOS transistor when the MOS transistor (T1) is on and the MOS transistor (T2) is off.

First, a pulse of about 24V positive than VSS is applied using the signal (M), and the MNOS transistors (MT, ) and (M
It is assumed that the gate threshold value of T2) is moved in the positive direction and set to approximately -2V.

In this state, a pulse of approximately 24V more negative than ss (+12), that is, a pulse of -12V is applied by the signal (M).

As a result, a voltage of approximately -24V is applied to the insulating film of the MNOS transistor (MT, ), and the gate threshold of the MNOS transistor (MT1) moves in the negative direction, approximately -
It becomes 8V.

On the other hand, since the channel potential directly under the gate of the MNOS transistor (MT2) is -6VL, approximately -6VL is not applied to the insulating film of the MNOS transistor (MT2), thereby preventing the gate threshold from changing.

In this way, the contents of the flip-flop are stored non-volatilely as the gate threshold of the MNOS transistor.

When energized, the MOS transistor (T3),
(T4) is working. In order to read the contents of the MNOS transistor stored as described above, the MOS transistor ('ra
) and ('r4) are both turned off.

When MOS transistors (T3) and (T4) are turned off, there is no load on the flip-flop, and M
Only the memory effect due to the gate capacitance of the OS transistors (T1) and (T2) remains.

Although the charge due to this capacitance varies depending on the value of the stray capacitance and the size of the gate threshold, it is gradually lost due to the leakage current of the p-n reverse junction.

When the remaining charge potential becomes almost O, the signal (M
), gradually applying a negative potential from ■ss to the MNOS transistor with the lower gate threshold (in this case, M
The NOS transistor (MT2) turns on first.

Therefore, from VSS to MNOS transistor (MT2)
Since a negative voltage is first applied to the source of the MOS
The transistor (T1) turns on, and the MOS transistor (
T2) is turned off and the contents previously stored in the MNOS transistor are read out.

Therefore, by detecting whether the power is on or off and controlling the signal (M), the contents of the flip-flop can be changed to the MNOS transistors (MT1), (MT
2), and the stored contents can be read out when the power is turned on.

The present invention is based on the above principle, in which a predetermined number is preset in advance by externally applying a signal to write the contents of the flip-flop to non-volatile memory, and thereafter counting is performed regardless of the contents of the non-volatile memory. is executed, and when the counter overflows, the preset number stored in the memory is read out to the flip-flop, and thereafter counting is continued from this preset number again.

The n-ary counter according to the present invention uses the circuit shown in FIG. 1 as one bit, and incorporates four bits to form one decimal digit, which are arranged in the number corresponding to a desired count value.

FIG. 2 is a diagram showing one decimal digit of the n-ary counter of the present invention.

In other words, one digit consists of 4 bits of the circuit shown in Figure 1 arranged, and this one digit includes an input control circuit 1, a reset and carry circuit 2, a carry circuit 3, a timing pulse generation circuit 4, and a set number of circuits. A modification circuit 5 is provided.

In this figure, the signals M, j, VDD, ■ss are the same as the signals shown in FIG.
This is a control signal for inhibiting count input when writing information to the OS transistor.

In addition, the signal R output from the timing pulse generation circuit 4
is a reset signal for resetting the circuit.

Furthermore, the output signals IN and IN of the input control circuit 1 are input signal signals Qh t1 to the first stage flip-flop circuit.
1Q2, (g)2:Q3 7Q are the output signals of the flip-flops in each stage, and are simultaneously input signals to the flip-flops in the next stage.

In this figure, the carry circuit 3 has exactly the same configuration as that provided in a conventionally known MOS flip-flop circuit, and the input control circuit 1 and the reset and carry circuit 2 also have a switch function to interrupt counting. has exactly the same configuration as the conventional one.

Further, the timing pulse generating circuit 4 outputs each signal M, Oka, and R according to the timing shown in FIG.

Furthermore, the set number changing circuit 5 is constituted by a switch mechanism as shown in FIG.

Next, the operation of this n-ary counter will be described.

First, turn the switch 51 of the setting number changing circuit 5 to the terminal and apply a positive voltage of about 24 V from the substrate potential ■ss (+12■) of the MNOS transistors MT1 and MT2 to apply the signal M.
Erase the NOS transistor.

At this time, the gate threshold values of the MNOS transistors MT1 and MT2 become approximately -2.

Next, switch the switch to terminal 3 and set the signal M to ±12V.

At this time, the other switch 52 is set to the terminal to set the signal 7 to the ground level Ov, and the switch 53 is set to the terminal - to set the signal RS to the -ss level (+12V).

In this state, a count input pulse is applied to the input control circuit 1, and the count content is the complement of n (in this case, for example, if a hexadecimal counter with n = 6 is configured in the counter 1 that can count from 0 to 9, n The complement of is 4(
= 10-6)), switch the signal M to the terminal ■ and set the signal M to a voltage that is about 24V more negative than VSS.
12 ■.

As a result, for example, when T1 is on and T2 is off, a write voltage is applied to the memory transistor MT, and its gate threshold moves negatively to approximately -8.

On the other hand, in the memory transistor MT2, since T2 is off, a voltage of VDD appears directly under the gate of MT2, and writing is prohibited.

In this way, the writing is completed and the complement of n is set in a non-volatile manner.

Next, each switch in the set number changing circuit 5 is turned to the timing pulse generating circuit 4 side, that is, to the terminal 2, and n-ary counting is performed, but before the n-ary counting begins, the nonvolatile memory is first read.

That is, the timing pulse generating circuit 4 raises the signal V to VSS (+12V) as shown in FIG.
1. After destroying the contents of T2, gradually lower the signal M from the VSS level to the ground potential.

As a result, as described above, since the gate threshold of MNOS transistor MT2 is lower, MNOS and MT2 start conducting earlier than MT1, charging stray capacitance C1, turning on MOS transistor T1, and turning off MOS transistor T2.

Thereafter, when the signal M is raised to the VSS level and the signal 7 is lowered to the original ground potential, the contents of the nonvolatile memory are read back to the flip-flop.

After that, when a count input is continuously applied, the flip-flop counts up using the complement of n as an initial value.

Counting continues and when the counter overflows, the carry circuit 3 outputs a carry signal.

This carry signal is applied to the timing pulse generation circuit 4, and upon receiving this signal, the timing pulse generation circuit 4 again outputs the signals M, φ, and RS shown in FIG. 3.

Therefore, the count number returns to the complement of n after overflowing.

By repeating such operations, this counter performs n-ary operations.

Next, a case will be described in which the number n that has been set once is changed.

When changing n, each switch in the set number changing circuit 5 is separated from the timing generating circuit 4.

Then, in the same way as in the first writing, switch 51 is turned to terminal ■ to erase the contents of the MNOS transistor, and then switched to terminal ■, switch 52 is changed to terminal ■, and switch 53 is changed to terminal ■.

In this state, a count input pulse is applied to the input control circuit 1, and when the number reaches the changed complement of n, the switch 51 is switched to the terminal ■.

As a result, the modified n's complement is stored in the MNOS transistor in a non-volatile manner.

Thereafter, each switch in the set number changing circuit 5 is connected to the timing pulse generating circuit side to operate as an n-ary counter.

FIG. 4 is a diagram showing each input/output signal when the n-ary counter of the present invention is integrated.

This counter has four decimal digits, but since it is constructed so that the digits can be assigned by an oscillator, the output is a BCD output for only one digit.

In this figure, signal CI indicates a count input, signal CC indicates a count clear input, signal SI indicates a scan input, signal RS indicates a restore signal, and signal CO indicates a carry output.

This 4-digit decimal counter can count from 0 to 9999, but let us consider a case where it is converted into a ternary counter.

In this case, the complement is 9997 (-10000-3), so after adding 9997 count inputs, this number is written into the MNOS transistor.

If 9997 is the initial value and then two pulses are added, the value becomes 9999.

Then, when the third pulse is added, the next count will be 00.
At this time, the carry signal (overflow signal) output from the carry circuit 3 causes the timing pulse generation circuit 4 to output each signal shown in FIG. 2, and the non-volatile memory is read out and the counter is The content is forcibly set to 9997.

Therefore, this counter is 9997, 9998, 999
It becomes a ternary counter that repeatedly counts the three values of 9.

Similarly, if 9998 is written in a nonvolatile manner, it becomes a binary counter, and if 0000 is written, it becomes a decimal counter.

Therefore, by writing data into the MNOS transistor using the setting number changing circuit, it is possible to make any n-ary counter from binary to 10,000.

As described above in detail, the n-ary counter of the present invention allows n to be arbitrarily changed using the same wiring, so unlike the conventional n-ary counter, there is no need to change the connections, making it extremely versatile.

In addition, there is no need to derive output and input terminals from each bit as in the past, and only one feedback loop is required to feed back the carry signal, which is very convenient for integration and increases capacity. can be achieved.

Furthermore, according to the present invention, n can be easily set, and n can be easily changed electrically even while the counter is in operation, and there is no need to worry about falling into a combination prohibited state as with conventional n-ary counters. It can be operated safely without any problems.

In the embodiments of the present invention described above, an MNOS transistor is taken as an example of a non-volatile memory, but the present invention is not limited to this, and it may be a MIOS structure or a MIS structure that stores information non-volatilely in an insulating film. Good to have,
Alternatively, a material that can be erased with ultraviolet light or the like and written electrically may be used.

Further, in FIG. 3, the configuration of the set number changing circuit 5 is shown as a simple switch mechanism to simplify the explanation, but this switch mechanism can be configured with an electric circuit using, for example, a transistor.

Also, the MNOS transistor MT in the circuit shown in FIG.
,, T8 is provided in addition to the switching element T7 between MT2 as shown in FIG. 5a, and this is further modified as shown in FIG. 5b so that T8 and T complete the discharge You may.

Furthermore, as shown in Figure 4, if a count clear signal can be added, once the count is cleared and the count is started, it will work as a counter different from the set n-ary, and the contents of the memory transistor will be read out in the middle. It can also be used as an n-ary counter.

Furthermore, two n-ary counters can be realized on the same chip by connecting another nonvolatile memory transistor in parallel to each nonvolatile memory transistor and applying the signal M independently to each pair of memory transistors.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing only one bit to explain the operating principle of the n-ary counter of the present invention, FIG. 2 is a circuit configuration diagram showing an embodiment of the n-ary counter of the present invention, and FIG. 3 is a diagram showing the output signal waveform of the timing pulse generation circuit in FIG. 2, FIG. 4 is a diagram showing the input/output terminal when the n-ary counter according to the present invention is integrated, and FIGS. 5 a and b are diagrams. FIG. 7 is a diagram showing another embodiment of the n-ary counter of the present invention. MT,, MT2...MNOS transistor, T
1~T,...MOS transistor, 1...
... Input control circuit, 2 ... Reset and carry circuit, 3 ... Carry circuit, 4 ... Timing pulse generation circuit, 5 ... Setting number change circuit.

Claims (1)

[Claims] 1. A plurality of flip-flops each comprising a pair of cross-connected transistors and a load connected to each of these transistors and constituting each bit of a binary code, each of which is interposed and connected between the pair of transistors and the load. a non-volatile field effect memory transistor, a switching element connected in parallel to each of these memory transistors, circuit means for causing the plurality of flip-flops to perform a counting operation based on an input signal, and circuit means for writing the complement of the count number n to be set into the memory transistor; circuit means for reading out the plurality of numbers written in the memory transistor into the flip-flop and closing the switching element to start a counting operation; an n-ary counter comprising circuit means for reading the complement information stored in the memory transistor to the flip-flop each time the memory transistor overflows, and for repeating the counting operation by closing the switching element.