JPS589618B2 - Data transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission system for transmitting data between a plurality of terminal devices and a central device using a common data bus.

In a system where data is transmitted between multiple terminal devices and a central device using a data bus common to each terminal device, it is necessary to avoid sending data from multiple terminal devices to the common data bus at the same time. Must be.

FIG. 1 is a system diagram showing an overview of a conventional data transmission system of this type, in which 1 is a central device, 2 is a terminal device, 3 is a common data bus, and 4 is an inhibit line.

That is, in FIG. 1, in order to avoid multiple terminal devices starting data transmission at the same time, the priority order of data transmission is determined by connecting the terminal devices 2 to each other via terminals Pi and Po. .

Furthermore, in order to prevent data from being sent from another (higher priority) terminal device while a certain terminal device is sending data, an inhibit line 4 commonly connected to the terminal INH of each terminal device 2 is provided. In contrast, an inhibit signal is sent from the terminal device that is currently sending the data.

In other terminal devices, data transmission is prohibited while the inhibit signal is arriving via the inhibit line 4.

Note that the terminals A1 to An are used to specify address information to be sent from each terminal device 2 to the common data bus 3 via the terminal DATA along with the data signal in order to identify the data sent from each terminal device 2. It is a terminal.

As is clear from the above, in the conventional system, in order to avoid sending data from multiple terminal devices at the same time, two terminals Pi and Po are used to give priority to each terminal device 2.
and one terminal INH for sending out an inhibit signal.
, a total of three terminals were required.

However, such an increase in the number of terminals not only occurs when each terminal device is composed of a large number of individual components, but also when it is integrated into an LSI, resulting in complicated interconnections, decreased reliability, and
Furthermore, it brings about problems such as price increases, and especially when trying to convert it into an LSI, due to the limitations of the LSI package,
In some cases, it may be impossible to provide all three terminals.

The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a data transmission system that can avoid simultaneous transmission of data from a plurality of terminal devices using a minimum number of terminals.

In order to achieve the above object, the present invention uses unique address information given to each terminal device in advance to identify data from each terminal device, and equally gives priority to data transmission. This is what I did.

That is, in this invention, when transmitting data from any terminal device, an inhibit signal is generated at a timing individually assigned to each terminal device in advance and transmitted to the inhibit line, and the inhibit signal is transmitted to the inhibit line. When an inhibit signal exists, generation of the inhibit signal is prevented, thereby allowing only one arbitrary terminal device to send data.

In this way, in order to avoid simultaneous data transmission, only one terminal for transmitting and receiving the inhibit signal is required.

Therefore, it not only simplifies wiring, but also improves reliability, reduces cost, and is advantageous when converting the device into an LSI, which has great effects.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 2 is a block diagram showing an outline of an embodiment of the present invention. As in the case of FIG. 1, 1 is a central device 2 is a terminal device;
is a common data bus, and 4 is an inhibit line.
Terminals P i and Po for priority specification in the figure
And there is no connection between them.

Each terminal device 2 has a built-in timing generating circuit 5 which has a function of transmitting an inhibit signal at the above-described timing when transmitting data.

A specific example of this timing generation circuit 5 is shown in FIG.

The timing generation circuit 5 of FIG. 3 will be explained below with reference to the time chart of FIG. 4.

It is assumed that the terminal 6 is connected to another circuit (hereinafter referred to as main circuit) within each terminal device 2.

In FIG. 3, a counter 11 counts a clock signal S1 from the main circuit and is cleared by a clear signal S2.
, 13, an AND gate 14 and an R-S flip-flop 15, each time the output value of the counter 11 reaches a constant value, the OR gate 1 is activated for one clock period.
6.

Once the inhibit signal is sent from any terminal device or after all the terminal devices are initialized at the same time, the normal generation timing of the clear signal S2 is determined by the timing generation circuit in all the terminal devices 2. 5 is common.

The comparator 17 compares the address values a1 to an of the terminal device given in advance via the terminals A1 to An with the output values b1 to bn of the counter 11, and when they match (a=b), inhibits It outputs a timing signal S3 that gives the signal generation timing.

Since the address value is different for each terminal device 2, the output timing of this timing signal S3 (the time T from when the clear signal S2 is generated until the timing signal S3 is generated) is a unique timing according to the address value. That's it.

The output timing of the timing signal S3 in the timing generation circuit 5 in each terminal device 2 is shown in FIG.
...Indicated as S3n.

The timing signal S3 thus obtained is applied to the clock input terminal of the D flip-flop 18 to which the data output request signal S4 from the main circuit is input.

Therefore, when the data output request signal S4 is input, the D flip-flop 18 is inverted at the timing determined by the timing signal S3, and sends the data output ready signal S5 from its output terminal to the main circuit.

The sending of the data output ready signal S, continues until the data output completion signal S6 is input from the main circuit to the clear terminal of the D flip-flop 18.

The data output ready signal S5, which is the output of the D flip-flop 18, is further applied to the buffer gate 19 and the terminal IN.
H to the inhibit line 4 in FIG.

This prohibits data transmission from other terminal devices.

That is, in FIG. 3, when an inhibit signal is input from the inhibit line 4 to the terminal INH, the inhibit signal is supplied to the main circuit as the data output request inhibit signal S7 via the inverter 20, thereby inhibiting data transmission. It turns out.

Further, this signal S7 is given as a clear signal S2 to the counter 11 via the OR gate 16 to clear the counter 11 and stop the counting operation until the inhibit signal sent from the other terminal device is released. .

That is, when an inhibit signal is present on the inhibit line, the generation of the data output ready signal S is prevented, thereby preventing the generation of the inhibit signal.

As explained above, in this invention, when data is sent from any terminal device to the common data bus, an inhibit signal is sent to the inhibit line at a timing specific to a predetermined address for each terminal device. Since simultaneous data transmission from a plurality of terminal devices is avoided while giving equal priority at the start of data transmission, the number of terminals provided on the terminal device can be reduced.

Therefore, it is extremely effective in actually configuring a system.

[Brief explanation of drawings]

FIG. 1 is a system diagram for explaining a conventional data transmission system, FIG. 2 is a system diagram for explaining an overview of an embodiment of the present invention, and FIG. 3 is a concrete diagram of the timing generation circuit in FIG. 2. A circuit diagram showing an example, and FIG. 4 are time charts for explaining the operation. 2...Terminal device, 3...Common data bus, 4...Inhibit line, 5...Timing pulse generation circuit.

Claims (1)

[Claims] 1. An inhibit line is commonly connected to multiple terminal devices that transmit data via a common data bus, and while an inhibit signal is being received from another terminal device via this inhibit line, the inhibit signal is sent out. In a data transmission method that prohibits the transmission of data from terminal devices other than the terminal device in use, each terminal device generates an inhibit signal at a timing individually assigned in advance to transmit data to the inhibit line. A data transmission system comprising: means for transmitting the inhibit signal; and means for preventing generation of the inhibit signal when the inhibit signal is present on the inhibit line.