JPS5910068B2 - bipolar logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a bipolar logic circuit in which an epitaxial layer is provided on a semiconductor substrate and has an emitter region, at least one additional collector region and one output collector region in this layer. Related to circuits.

Such logic circuits are known and are described, for example, in the publication IEEE Engineering 974 International Conference on Solid State Circuits, p. 18 and Eng. 9:
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A bipolar CHL circuit is described under the title ``Y''.
The CHL element shown in FIG. 1 is primarily a pnp transistor with an additional collector Cl between the emitter E and the output collector Co. When current flows between the emitter and the output collector, this CHL element
Acts as an np transistor. However, when the control collector Cl has a negative bias voltage with respect to the emitter E, the control collector Cl absorbs the charge carriers previously collected in the output collector Co, and only the reverse current flows from the emitter E to the collector Co. will flow. Furthermore, an additional collector C' is provided, which is connected to the substrate and thus has the purpose of preventing charge carriers from diffusing out of the control collector Cl.

Such a CHL element provides V) NOR gates and NAND
A gate can be configured. Literature “lntegra
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Volume SC-7, Ya 5, October 1972, 346-351
A functionally integrated 12L basic circuit with lateral Pnp transistors and vertical Npn transistors with inverted operation is known.

The aim of the invention is to increase the integration density compared to known circuits.

This object is achieved according to the invention by the arrangement defined in claim 1.

An important advantage of the invention is that, due to the fully functional integration of the output stage, approximately only one area is required.

An advantage of this invention is that, as in known CHL circuits,
The advantage is that no isolation/diffusion section or insulation process is required.

The advantage is that space is saved compared to known L2L arrangements (by virtue of the ability to create basic circuits).

The invention will now be explained with reference to the drawings.

FIG. 1 shows an equivalent circuit of an NCR gate with two outputs according to the present invention, and FIG. 2 shows a layout of the NCR gate shown in FIG.
Figure 3 shows the first type where two collectors are gathered into one diffusion region.
FIG. 4 shows the layout of the circuit of FIG. 3.

FIG. 1 shows an NCR gate according to the invention consisting of a lateral Pnp transistor and a vertical Npn transistor 2 of inverted operation.

The emitter of transistor 1 is connected to line 3. It is best to apply a constant power supply current through this line. transistor 1
It is better to ground the base 12 of. 13 and 14 are the control collectors of the transistor 1, 15 is its output collector, and 15 also forms the base of the vertical Npn transistor 2.

The emitter 23 of the transistor 2 is preferably grounded. Terminals 21, 22 represent the output of transistor 2, hereinafter referred to as output transistor. FIG. 2 shows the technical structure of the NOR gate of FIG.

An epitaxial layer 4 is provided on a Si substrate (not shown). It is preferable that there is a buried layer between this epitaxial layer and the substrate. This buried layer has the purpose of compensating for potential differences in the epitaxial layer. The epitaxial layer 4 simultaneously forms the base region 12 of the lateral Pnp transistor and the emitter region 23 of the vertical Npn transistor of inverted operation.

This layer is preferably n-doped. The p-type doped regions contained in this epitaxial layer are shown shaded. The areas indicated by dots are contact holes. Components in FIG. 2 that have already been described with respect to FIG. 1 are provided with corresponding reference numerals. As can be seen in FIG. 1, the base region 12 of the lateral Pnp transistor as well as the emitter region 23 of the vertical output transistor are at the same potential, in particular at ground potential, so that it is advantageous that the components are well isolated from each other. It is.

The elimination of isolation with this invention results in space savings of approximately 70% compared to conventional CHL circuits. The collector 6 arranged in the epitaxial layer absorbs excess charge carriers.

This collector should be grounded. Next, the operation of the NCR gate according to the present invention shown in FIGS. 1 and 2 will be explained.

The emitter 11 of the lateral Pnp transistor is connected via line 3 to the positive potential of the supply voltage. transistor 1
The base 12 and the emitter 23 of the output transistor are grounded. The emitter 11 injects holes into the n-type epitaxial layer with the base 12 when the supply voltage +UB is applied. While the potential of the collector 13 is below the potential of the emitter 11, at least some of these holes are absorbed by the collector 1.
Absorbed by 3. When the collector 13 is open, it is charged to a positive potential due to absorption of holes until the holes are injected back into the epitaxial layer. The holes are then absorbed by the collector 14. In this case, charging and hole injection occur again when the collector 14 is open, so that when the collectors 13 and 14 are open, the collector 15
A current is generated that leads to. Collector 15 simultaneously moves in vertical direction N
Since it forms the base of the pn output transistor 2, current flows to the ground terminal at this time. That is, it can be seen that when the collectors 13 and 14 are open, the Pnp transistor 1 is conductive and the outputs 21 and 22 of the output transistor 2 are pulled to the ground potential. However, once the collector 13 or 14 is grounded and therefore carries a current, the collector 15 is currentless and the output transistor 2 is blocked. Output 21, 22
Only a reverse current can still flow through . Output 21
, 22 (current present or absent) corresponds to the NCR logical combination of the states of the collectors 13, 14 which serve as human power.
To construct a corresponding NOR gate with a lateral Npn transistor hexagram and a vertical Pnp transistor with inverted operation, the doped entire hexagrams and regions according to FIG. 1 and FIG. 2 are doped in the opposite way as described above. do.

Corresponding to the document mentioned at the outset, it is also possible to create a NAND gate with a suitable arrangement of the emitter regions.

For example, due to the configuration of such a gate, the number 13 in FIG.
The collector shown at 14 is omitted and the collector shown at 14 is divided into two juxtaposed collectors. This corresponds to the collectors Cl and C2 in the BIIC diagram in FIG. 2 of the above-mentioned document. The circuits of FIGS. 3 and 4 have the advantage, compared to the circuits of FIGS. 1 and 2, of achieving a particularly small circuit structure and thus of a greater integration density.
3 and 4, according to the present invention, the collectors 14 and 15 of FIG. 1 are replaced by the transistors 14 and 15 of FIG.
0 base area 150VC total. Therefore, the function of the circuit remains unchanged. This is because the output transistor 20 can be blocked by current removal to the collector 130 or to the collector 150 which is at the same time the base region. The arranged collector 60 serves to absorb excess charge carriers.

This collector should be grounded.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, and FIG. 1 shows an equivalent circuit of an NCR gate with two outputs, and FIG. 2 shows its layout.
FIG. 3 shows the circuit according to FIG. 1 in which two collectors are gathered in one area, and FIG. 4 shows its layout. In the figure, 1 and 10 are lateral transistors, 220 is a vertical transistor, and 4 and 40 are epitaxial layers.

Claims (1)

[Claims] 1 Lateral pnp in an epitaxial layer on a semiconductor substrate
(npn) transistor and inverting operation vertical n
A bipolar logic circuit with a pn (pnp) transistor, in which the lateral transistor 10 has a p(n) doped collector which also forms the p(n) doped emitter region 110 and the base of the vertical transistor 20. The epitaxial layer 40 has a region 150 forming the base of the lateral transistor 10 and the emitter of the vertical transistor 20, and has an n(
p) doped output collector regions 210, 220 are embedded, emitter region 110 and epitaxial layer 40;
A supply voltage is applied between and an additional p(n)-doped collector region 130 is provided between the emitter region 110 and the p(n)-doped collector region 150 in the epitaxial layer 40, which in which a terminal is used as a first control input, p
(n) A bipolar logic circuit, wherein the doped collector region 150 has a terminal that is used as a second control input. 2. Bipolar logic circuit according to claim 1, characterized in that a further p(n)-doped collector region 60 of the lateral transistor 10 is provided.