JPS5910083B2 - transistor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a source follower circuit or an emitter follower circuit using field effect transistors or bipolar transistors, and particularly to improvements in gain efficiency, transmission characteristics, and stability in DC operation.

FIG. 1 is an example of a source follower circuit using conventional field effect transistors.

Q1 is a field effect transistor (hereinafter referred to as FET) with saturation characteristics that constitutes a source follower circuit.

The gate of this FETQ1 is connected to the input terminal IN and grounded via the resistor R1, and the drain is connected to the resistor R2.
The source is connected to the negative power source -■ through a variable impedance circuit consisting of a bipolar transistor Q3 and a resistor R4, and is connected to the output terminal OUT through a capacitor C1. has been done.

This output terminal OUT is grounded via a resistor R6.

Q2 is a FET with saturation characteristics, the gate of FETQ2 is connected to the drain of FETQ1, the drain is connected to a positive power supply +V, and the source is connected to a resistor R3 connected in series.
．． They are connected to negative polarity power supply 1 through R, respectively.

The FET Q2 and the resistors R3 and R constitute a feedback circuit, and the signal appearing at the drain of the FET Qt is transferred from the connection point between the resistors R3 and R of the feedback circuit to the transistor Q3 of the variable impedance circuit. applied to the base.

That is, the signal sent from the drain of FETQ1 is negatively fed back to the source of FETQ1 via the feedback circuit and variable impedance circuit.

Further, the resistors R3 and R5 of the feedback circuit function as DC level shifting means for matching the DC level between the drain of FET QI and the base of transistor Q3 of the variable impedance circuit.

By the way, the conventional source follower circuit described above has a resistor R3 as a DC level shift means in the feedback circuit.
R, also attenuates the signal, and F E T Q
1 cannot be given sufficient negative feedback.

It is clear that this does not make full use of the so-called negative feedback effect of the entire transistor circuit, which hinders improvements in stability, distortion characteristics, etc. The purpose of the present invention is to provide a transistor circuit that improves the gain efficiency by improving the DC level shifting means of the transistor, and also has excellent transmission characteristics, stability of DC operation, and temperature characteristics.

That is, in the transistor circuit of the present invention, an input signal is applied to the gate, the drain is connected to a positive polarity power source via a constant current source, and the source is connected to one fixed terminal of a potentiometer, and the input signal is applied from the movable terminal of this potentiometer. a FET main transistor configured to take out a source follower output signal; and a first FET auxiliary transistor having the same power characteristics as the main transistor, the gate of which is connected to the drain of the main transistor, and the drain of which is connected to the positive power supply. and a second bipolar auxiliary transistor having a base to which a predetermined DC potential is applied, an emitter connected to the source of the first auxiliary transistor through a resistor, and a collector connected to a negative power supply through a resistor. a third bipolar auxiliary transistor having a base connected to the collector of the second auxiliary transistor, an emitter connected to the negative power supply via a resistor, and a collector connected to the other fixed terminal of the potentiometer. The present invention is characterized in that a sufficient amount of negative feedback is applied to the source follower operation of the main transistor, and non-linear distortion in the input/output characteristics of the main transistor is canceled out.

The present invention will be explained below based on the embodiment shown in FIG.

Qt (main transistor) is a FET with saturation characteristics that constitutes a source follower circuit like Q1 in the circuit shown in Figure 1.
It is.

The gate of this FETQ1 is connected to the input terminal IN and is also grounded via a resistor R1.

The source of the FET Q1 is a potentiometer Rv,
Bipolar transistor Qa-Qs, resistor R3
, R4, and R5 to the negative polarity power source 1-2 through a variable impedance circuit.

The sliding tap of the potentiometer Rv is connected to the output terminal OU.
Connected to T.

The drain of the FET Q1 is connected to a positive power supply +■ via a transistor Q4 and a FET Q5 with saturation characteristics.

Further, the FET Q5 serves as a drain load for the FET Q1, and the gate and source of the FET Q5 are connected, and the FET Q5 operates at a constant current, supplying a substantially constant current 11 to the FET Q1.

Therefore, the drain load impedance of F E T Ql remains very high and approximately constant, and the input signal is amplified with a very large gain and appears at the collector of transistor Q4.

The transistor Q4 constitutes a bootstrap circuit together with the resistor R2.

In other words, F E T Q6 has its gate and source connected and operates at a constant current.
A substantially constant current 12 is supplied to resistor R2 via TQ6, creating a substantially constant voltage drop across resistor R2.

Thus, the base potential of transistor Q4 prevents the drain-source voltage of FET QI from being modulated (varied) by the input signal applied to input terminal IN.

That is, due to the bootstrap effect on the transistor, the drain-source voltage of FET Q1 is kept almost constant regardless of the input signal, and the gate leakage current of FET Q1 is kept at a low constant value.

The drain output signal of FETQ1 (opposite phase to the input signal) is applied to the gate of FETQ2.

This FETQ2 (first auxiliary transistor) is FETQ2 (first auxiliary transistor)
T has the same transmission characteristics as Qt, and transistor Q7
, resistor R7 - RB + Rg constitute a feedback circuit, the source of which is resistor R6 and transistor Q
7. It is connected to the negative polarity power supply -■ through the resistor R, and its drain is connected to the positive polarity power supply +■.

The transistor Q7 (second auxiliary transistor) is a bipolar transistor whose base is connected to the resistor R7.
It is connected to the positive power supply +■ through the resistor R, and is held at a predetermined potential and grounded through the resistor R8, and its collector is connected to the negative power supply -■ through the resistor R, which is the so-called base. It constitutes a grounding circuit.

A resistor R6 is connected to the emitter of this transistor Q7.
The source signal of the FETQ2 is applied through the FETQ2.

In other words, the FET Q2 and the transistor Q7 are connected in cascode.

The drain output signal of the FET Q1 is fed back to the base of the transistor Q8 of the variable impedance circuit through a feedback circuit composed of the FET Q2 and the transistor Q7.

The common base circuit consisting of the transistor Q7 of the feedback circuit shifts the DC level of the signal at the source of the FET Q2 to match the DC level of the transistor Q3 without attenuating the output signal at the source of the FET Q2. .

This transistor Q3 (third auxiliary transistor) is
which constitutes the variable impedance circuit, the collector of which is connected to FET via the potentiometer Rv.
It is connected to the source of Q1, its base is connected to the collector of transistor Q7 of the feedback circuit, and its emitter is connected to negative power supply voltage 1V via resistor R4 and transistor Q8.

A constant voltage determined by a resistor R3tR5 is applied to the transistor Q8, and the transistor Q3
Regardless of the input signal at the base of this transistor Q
The emitter potential of No. 3 is held constant.

The signal from the feedback circuit changes the collector resistance of transistor Q3, which causes FET to be applied to the source of FET Q1.
The drain output signal of ETQ1 is fed back in reverse phase.

That is, the drain output signal of FETQI is transmitted to this FETQI via a feedback circuit and a variable impedance circuit.
Negative feedback is provided to the source of Q1.

Furthermore, by using FETQ2 and FETQ that are selected as a pair from the viewpoint of transmission characteristics, these FETQ2 and FETQ
If E T Q1 and Q2 are configured with the same transfer characteristics, the non-linear distortion of the input/output characteristics inherent to these field effect transistors can be almost completely canceled out from each other.

Note that the potentiometer Rv is provided to adjust the DC potential of the output terminal OUT to the ground potential.

It is now known that the drain current IDSS of FETQ5-Qa has a certain inherent value and hardly changes depending on the ambient temperature.

For example, in the case of Sony 28K-43, the drain-source voltage VDS"10■, the gate-source voltage VC}
As shown in FIG. 3, the drain current IDSS when s=ov is constant at a specific value IP regardless of the ambient temperature.

Therefore, if the drain current IDSS of FET Q-, -Qa is selected to a value that is not affected by the ambient temperature, the voltage drop across the potentiometer Rv is (s 1 +
12) Rv, which remains constant regardless of the ambient temperature, and the output terminal OiJT can be held at ground potential.

Furthermore, since F E T Q5 and Qa perform constant current operation, the current (tl+t2) flowing through the potentiometer Rv can be kept almost constant even when the power supply voltage +V fluctuates, and the output terminal OUT can be kept at a constant current. can be held at ground potential regardless of fluctuations in

Therefore, it is extremely effective when used in applications that require DC input and DC output, such as interface circuits for measuring instruments, etc. Moreover, it eliminates glue actance elements such as the output capacitor C1 of the conventional transistor circuit shown in Figure 1. Therefore, the transient characteristics etc. are also extremely good.

As stated above, the transistor circuit of the present invention is
Since a common base circuit using a transistor is used as the level shift means in the feedback circuit, the signal components can be transmitted faithfully without attenuation, and the IIL current level can be shifted appropriately, so the gain efficiency can be improved by applying sufficient negative feedback. ,
It has excellent effects such as improved transmission characteristics such as distortion rate and frequency characteristics, and high stability against fluctuations in temperature and power supply voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional source follower circuit, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional source follower circuit.
FIG. 2 is a characteristic diagram showing drain current versus temperature characteristics of a saturation characteristic field effect transistor. Q1... Field effect transistor forming a source follower circuit, Q2... Feedback field effect transistor, Q3... NPN transistor forming a variable impedance circuit, Q7... ... PNP type transistor for level shift, R1, ..., R,
······resistance.

Claims (1)

[Claims] 1. Consisting of a field effect transistor, an input signal is applied to the gate, the drain is connected to a positive polarity power source via a constant current source, and the source is connected to one fixed terminal of a potentiometer. A main transistor configured to take out a first follower output signal from a movable terminal of the main transistor, and a field effect transistor having the same output characteristics as the main transistor, the drain of the main transistor being connected to the gate, and the drain connected to the positive electrode. a first auxiliary transistor connected to an auxiliary power source, and a bipolar transistor, whose base is applied with a predetermined DC potential, whose emitter is connected to the source of the first auxiliary transistor via a resistor, and whose collector is connected to a resistor. a second auxiliary transistor, which is connected to the negative power source through a resistor; and a bipolar transistor, whose base is connected to the collector of the second auxiliary transistor, and whose emitter is connected to the negative power source through a resistor. , and a third auxiliary transistor whose collector is connected to the other fixed terminal of the potentiometer, to provide a sufficient amount of negative feedback for the source follow operation of the main transistor, and to control the input/output of the main transistor. A transistor circuit characterized in that non-linear distortion in characteristics is canceled out.