JPS591009B2 - hand dryer warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an integrated inj.
The present invention relates to semiconductor logic circuits that utilize the technology (ectionLogic).

FIG. 1 shows the structure and circuit of a conventional IIL.

First, N+
A layer (ρ5-10 to 16Ω/mouth) 11 is formed, and 1
An N-evidential layer 12 of the order of 0.016 atoms/crit is grown.

Next, one layer of boron etc. of about 1019 at oms/d
10 is selectively diffused into this P layer 13.
Approximately 20a t oms/ant of phosphorus etc. is added to the N layer 15,
Selectively diffuse as 16.

1 to further reduce the contact resistance of the first layers 13 and 14.
In some cases, 77 layers of boron or the like are formed in the P layer as, for example, the vinyl layer 17.

In this way, the 11th layer becomes the emitter extraction layer of the switching NPN transistor Q1, the 12th layer becomes the emitter of Ql, and the base of the lateral PNP l-transistor Q2.

The 13th layer serves as the base of Ql and also serves as the collector of Q2.

The 14th layer is the emitter of Q2 and serves as a current injection port.

Furthermore, the 15th and 16th layers are Ql collectors and have multiple outputs.

Further, the 17th layer is added for the purpose of lowering the contact resistance between the 3rd layer and the A1 electrode 18.

FIG. 1 shows an equivalent circuit of FIG.

In FIG. 1, the same parts as in FIG. 1 are designated by the same reference numerals.

In the equivalent circuit shown in Figure 1, the base of Ql is connected to the IN terminal, the emitter of Q2 is connected to the Vc main power supply, the emitter of Ql and the base of Q2 are grounded, and the entire Ql
This is an inverter with the collector C1C2 as the output terminal.

However, the configuration of a complex logic circuit becomes complicated if only this inverter is used.

FIG. 2a shows a NOR gate using IIL.

A matching circuit that compares two signals and calculates the sum and difference of binary numbers is shown in Figure 2.

Here, A and B are input terminals OUT, and output terminal Vc is a power supply terminal.

Further, FIG. 2C is a block diagram of FIG.

If the inverter has one element, the number of elements will increase to 8.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, reduce the number of elements, and provide a semiconductor logic circuit for a coincidence circuit that can be easily constructed.

In the present invention, an OR gate or an AND gate can be easily configured by supplying the second input signal to the collector of the output transistor of the IIL via a Schottky diode.

An embodiment of the present invention will be described below with reference to FIG.

In Figure 3, ρ5-1 is placed on the P substrate (not shown).
0-16. A Q/hole N0 buried layer 30 is formed of antimony or the like, and an epitaxial layer 31 of about 1016 atoms/cril is grown in 30 layers.

Furthermore, the epitaxial layer 31 has 1018 atoms/cr.
N soil layer 3 with approximately iL of phosphorus etc. as N-WeII layer 36
0 lc'rfii, and further its N-W
Inside the eII layer 36 and the epitaxial layers 32, 33, 34,
Boron or the like of about 10"0 atoms/crrt each was placed in P'7m41 in 35.

Formed as 42, 43, 44, 45, and further shrimp layer 3
2.33.34.35, form N soil layers 37, 38, 39, and 40 with approximately 1020a tomy'd of phosphorus, etc.

If such a structure is adopted and the overall wiring is performed using a conductor 50 such as AI as shown in FIG. 3, (here, the wiring is shown as a space wiring because it is a schematic diagram, but the wiring is actually done on the 5i0251).

) The matching circuit shown in FIG. 3a is obtained.

In FIG. 3a, diodes D, , D2 are Schottky diodes, and the epitaxial layer 33 is AI-wired from the A input terminal A, and Dl is M-wired from the B input terminal B on the surface boundary 46 surrounded by the dotted line. D2 is formed on the epitaxial layer 34 and the surface boundary 47 surrounded by dotted lines.

In order to improve the diode characteristics, titanium or the like is placed under the AI of 46.47.

Next, the structure and operation of the matching circuit shown in FIG. 3a will be explained.

In FIG. 3a, input terminal A is connected to the cathode of Schottky diode D1 and the base of NPN transistor Q4, and input terminal B is connected to the cathode of Schottky diode D2 and the base of NPN transistor Q1.

Transistor Q1. Q2. Q4. Q5 is an NPN) transistor, and transistor Q3. Q6. Q7. Q8 is a PNP transistor, Ql and Q7, Q2 and Q3, Q4 and Q
8 and Q series 6 each constitute a pair of IILs.

The anode of Dl, the collector of Q3, the collector of Ql, and the base of Q2 are directly connected to each other, and the signal of A drives Q2 through Dl.

Further, the anode of D2, the collector of Q7, the collector of Q4, and the base of Q5 are directly connected to each other, and the signal of B drives Q5 through D2.

Next, the emitter of Q3, the emitter of Q6, the emitter of Q71, and the emitter of Q8 are connected to the Vcc power supply, and the base of Q3, the base of Q6, the base of Q7, the base of Q8, and the
The emitter of l, the emitter of Q2, the emitter of Q4, and the emitter of Q5 are grounded.

The collector of Q2 and the collector of Q5 are connected to the output terminal (OUT).

Next, the operation of this circuit is as follows.

Note that the base signal of Q2 is X, and the base signal of Q5 is Y.

■When A=0 and B=O, Dl is conductive and Ql is non-conductive, so X=0, D2 is conductive and Q4 is non-conductive, so Y=O
1 Therefore, Q2. Both Q5 are non-conducting, so the output terminal (O
UP) signal S=1.

■When A=1, B=O, Dl is non-conductive, Ql is non-conductive, so X21, D2 is conductive, and Q4 is conductive, so ¥20. Therefore, Q2 is conductive, Q5 is non-conductive, and S20. Become.

■When A=0, B21, Dl is conductive, Ql is conductive, so X=O1D2 is non-conductive, and Q4 is non-conductive, so Y=
1, therefore Q2 is non-conducting, Q5 is conducting, and s=o
becomes.

■When A=1, B21, Dl is non-conductive, Ql is conductive, X=O1D2 is non-conductive, and Q4 is conductive.'ry=o
.

Therefore, both Q2 and Q5 are non-conductive and S=1.

The above can be summarized as shown in the table below.

In this way, 5=AB+AB.

Also, only four elements are required.

Also, as is clear from this table, X=AB, Y2AB, and therefore the inverted output of the transistor Q1.
The outputs of Q5 are A1B and A1B, respectively.

That is, it can be seen that an AND gate or an OR gate can be constructed with a simple structure using IIL and a Schottky diode.

FIG. 4a shows the section switch circuit diagram shown in FIG. 3a, Ql, Q2. Q4 and Q5 are multi-collectors, one of each collector is connected in the same manner as in FIG. 3a, and the other one of each collector is used as an output end.

Furthermore, between input end B and the base of Ql, and between input end A and Q
The polarity is such that current flows toward the input end between the base of diode D3.4 and the base of diode D3.4. D4 is connected.

FIG. 4 shows that in the select switch circuit shown in FIG. 4a, the collectors of Q2 and Q5 are each placed in an impressive position, and these collectors are connected to their respective bases.

In this way, the charges accumulated in the base can be discharged to the collector, thereby improving the switching speed.

In FIG. 4C, in the sector switch circuit diagram shown in FIG. 4C, one collector is added to each of Ql and Q4, and these collectors are connected to their respective bases.

In this way, the switching speed can be further improved than that of the select switch circuit shown in FIG.

Furthermore, in the above description, it is clear that the P layer and the N layer may be reversed; in this case, the NPN transistor is changed to a PNP transistor, the anode is changed to the cathode, the cathode is changed to the anode, the positive power source is changed to the negative power source, and so on. Just replace each positive logic with negative logic (G).

As described above, according to the present invention, by using IIL in a semiconductor logic circuit for a coincidence circuit, it is possible to obtain a circuit that has a small number of elements, has a simple structure, and is suitable for an integrated circuit with low power consumption.

[Brief explanation of drawings]

Figure 1a is a sectional view showing the structure of a conventional IIL, Figure 1 is an equivalent circuit diagram of Figure 1a, Figure 2a is a conventional NOR gate circuit diagram, Figure 2 is a conventional NOR gate. FIG. 2C is a block diagram of FIG. 2, FIG. 3A is a circuit diagram of an embodiment of the present invention, and FIG. 3 is an integrated circuit of an embodiment of the present invention. Cross-sectional view of Figure 4 a, b
, c is a circuit diagram of an application example of the circuit diagram shown in FIG. 3a. A, B...Input terminal, OUT...Output terminal, Vc...Power supply terminal, Dl, D2...Diode, transistor between Q1 and Q8... .

Claims (1)

[Scope of Claims] 1. A first transistor of a first conductivity type having an emitter, a base, and a collector, the collector being the base of the first transistor, and the base being the first transistor. a second transistor of a second conductivity type, the emitter of which is connected to the power supply and forms an IIL together with the first transistor;
a Schottky diode having one end connected to the collector of the first transistor, a first input signal being connected to the base of the first transistor, and a second input signal being connected to the other end of the Schottky diode. A semiconductor logic circuit, characterized in that it obtains a logic output from each supplied output circuit connected to the collector of said first transistor. 2. The output circuit has an emitter, a base, and a collector, and a third transistor of the first conductivity type, the emitter of which is connected to the emitter of the first transistor, and the base of which is connected to the collector of the first transistor. , having an emitter, a base, and a collector, the emitter being connected to the emitter of the second transistor, the base being connected to the base of the second transistor, and the collector being connected to the base of the third transistor; 2. The semiconductor logic circuit according to claim 1, further comprising a fourth transistor constituting an IIL.