JPS591010B2 - tuner with clock - Google Patents

Description

[Detailed description of the invention] The present invention relates to a tuner with a clock.

A tuner that uses a frequency synthesizer and employs a digital frequency display usually has a 3-digit or 4-digit display, and in the domestic FM band, it is 6 m-6 m-shoulder.
,For foreign bands, it is displayed in the range of ■■・■～■68.9.

On the other hand, when considering a clock, for example, it is usually sufficient for daily life to display the time down to the minute, so whether it uses a 12-hour clock or a 24-hour clock, the digital display is
: ■4 digits like u are sufficient.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a tuner with a clock in which one display can be used for displaying the tuned frequency of the tuner and for displaying the clock by switching between the frequency display and the time display. This is the purpose.
Another object of the present invention is to provide a device that can double as a manual tuning device for the tuned frequency of the tuner as a time setting device for the clock display, when the tuner's tuned frequency display and clock display are shared by one display. The goal is to provide the following.

Embodiments of the clock tuner according to the present invention will be described below with reference to the drawings.

The output terminals of the tuner input circuit 11 and the clock input circuit 12 are coupled to the input terminal of a first switching circuit 13.

Although the tuner input circuit 11 and the clock input circuit 12 are shown as separate block diagrams for convenience of explanation, they may include circuits that are partially shared. The output terminal of the first switching circuit 13 has two output terminals, one of which is coupled to the up pulse input terminal of the first counting circuit 14 and the other one coupled to the down pulse input terminal of the first counting circuit 14. ing.

The output terminal of the first counting circuit 14 has two output terminals, one of which is connected to the up pulse or carry pulse input terminal of the second counting circuit 15, and the other to the down pulse or carry pulse input terminal of the second counting circuit 15. are respectively coupled to the pulse input terminals.

Similarly, the two output terminals of the second counting circuit 15 are connected to the up and down pulse input terminals of the third counting circuit 16, and the two output terminals of the third counting circuit 16 are connected to the fourth counting circuit 1?
are respectively coupled to the up and down pulse input ends of the.

Here, the first counting circuit 14 has a frequency of 0.1 MHz.
The second counting circuit 15 outputs an output signal for digital display of digits or 1 minute digit of a clock, and similarly outputs a signal for digital display of 1 MHz digit or 1 minute digit of a clock.
The third counting circuit 16 outputs an output signal for a digital display of minute digits, the third counting circuit 16 outputs an output signal for a digital display of 10 MHz or hour digits, and the fourth counting circuit 17 outputs an output signal for a digital display of 10 MHz or hour digits.
These are circuits for obtaining output signals for digital display of the 00 MHz digit or the 10 o'clock digit, and well-known techniques including other circuits attached thereto can be applied.

An up-down device for manual control is connected to each input terminal of the first counting circuit 14, the second counting circuit 15, and the third counting circuit 16, respectively. Said first
A first manual up pulse generation circuit 18 is connected to the up pulse input terminal of the counting circuit 14, and a first manual down pulse generation circuit 19 is connected to the down pulse input terminal of the counting circuit 14. A second manual up pulse generation circuit 21 is connected to each up pulse input terminal of the circuit 15 and the third counting circuit 16 via a second switching circuit 20, and a second manual up pulse generating circuit 21 is connected to each up pulse input terminal of the counting circuits 15 and 16. A second manual down pulse generating circuit 22 is connected via the second switching circuit 20. Note that the first switching circuit 13 and the second switching circuit 20 are mechanically or electronically interlocked.

That is, when the first switching circuit 13 receives the output of the tuner input circuit 11 and couples the first switching circuit 13 to the first counting circuit 14, the second switching circuit 20 switches to the second manual up pulse generating circuit. 21 and a second manual down parnu generation circuit 22 are coupled to the input terminal of the second counting circuit 15, and when the first switching circuit 13 couples the clock input circuit 12 to the first counting circuit 14, the second The switching circuit 20 switches the second manual up pulse generating circuit 21 and the second manual down pulse generating circuit 22 to the third counting circuit 1.
It is connected to the input end of 6. The first manual up and down pulse generating circuits 18 and 19 are controlled by a manual switch, such as a touch switch or a return switch, and this manual switch 18'
, 192 are provided below the least significant digit display portion 32 of the display 30, as shown in FIGS. 2 and 3, as shown in FIGS.

Similarly, control switches 21' and 22'' for the second manual assembly and down pulse generation circuits 21 and 22
is provided below the third digit display section 33 of the display 30. The basic structure of the watch tuner of the present invention is as described above, and its operation is as follows.

First, when the first switching circuit 13 has a function as a tuner, when the tuner input circuit 11 is connected to the first counting circuit 13 by being controlled from the outside by, for example, a switch, each of the counting circuits 14, 15, 16, 17 counts up to the frequency specified by a preset circuit (not shown), and for example, as shown in FIG.
z] is displayed on the display 30. On the other hand, in connection with the operation of the first switching circuit 13, the second switching circuit 20
manual attachment and down pulse generation circuit 21,
22 and the second counting circuit 15 are coupled.

The number of tuned frequency plates is changed by controlling the manual up pulse generation circuits 18, 21 or the manual down pulse generation circuits 19, 22.

If the switch 18' is operated once, the 0.1 MHz digit number will be increased by one unit, and if the switch 19' is operated once, the number will be decreased by one unit. Also, by operating the switch 21', the 1MHz digit number will be increased by 1 unit, and the switch 22' will be incremented by 1 unit.
'' can be decreased by 1 unit.

These changes in frequency display are, of course, instructions for changing the tuning frequency of the tuner, and the circuits and operations related to the same-air circuit are not directly related to the present invention, and therefore will not be described.

Next, by controlling the first switching circuit 13, the clock input circuit 1
2 functions as a clock coupled to the first counting circuit 14, each counting circuit 14, 15, 16, 17 and the display 30 no longer exhibit a clock function and the first and second
Abbot down pulse generation circuit 18, 19, 21, 22
The switches 18'', 192, 21'', and 22'' serve as clock display changing means.

That is, each counting circuit 14, 15, 16, 17 counts the time according to the input pulse from the clock input circuit 12.
As shown in the figure, the time 12:43 is displayed at that time, and the first counting circuit 14 obtains an output for digital display of the 1-minute digit, and the second counting circuit 15 obtains an output for the digital display of the 1-minute digit. 3
The counting circuit 16 obtains an output for digital display of the hour digit, and the fourth counting circuit 17 obtains an output for digital display of the 10 o'clock digit.

On the other hand, in conjunction with the switching of the first switching circuit 13, the second switching circuit 20 couples the second manual up-down pulse generating circuits 21, 22 to the third counting circuit 16. The clock display can be changed using the first manual up-down pulse generation circuits 18, 19 and operation switches 18', 19'.
and a second manual up-down pulse generation circuit 21
, 22 and operation switches 21', 22''. That is, by operating the switch 18', an up pulse is applied to the first counting circuit 14, and the minute digit number is increased by 1, and the switch 19 is operated. By operating ``, a down pulse is applied to the first counting circuit 14, and the minute digit number decreases by one unit. Also switch 21' or 22
By operating ', an up pulse or a down pulse can be applied to the third counting circuit 16 to increase or decrease the number in the hour digit by one unit. That is, in the above manner, the tuned frequency display of the tuner and the time or time of the clock can be displayed using a common display.

Therefore, the oscillation source used for the frequency synthesizer can also be used as the reference frequency oscillator for the watch, and in addition, the frequency divider and display drive circuit can also be used for both the tuner and the watch, which is rational and reduces costs. do. In addition, the tuner's frequency adjustment manual device, that is, the manual channel selection device, can also be used as a manual device for setting the clock time (changing the time, changing the time), and the switch can be positioned and operated in relation to the display. Effective for sex.

In addition, in the above embodiment, an example was shown in which the frequency each digit counting circuit for the tuner and the each digit counting circuit of the clock were shared, but the tuner and the clock are configured as separate circuits and the circuit that is shared is an oscillator. , a display, a display drive circuit, and a manual switch, and various aspects may be considered as to whether the specific partial circuits are shared or independent as a matter of design.

Therefore, as detailed above, according to the present invention, one display is shared for displaying the tuned frequency of the tuner and for displaying the time, such as by switching between the frequency display and the time display.
In particular, it is possible to provide an extremely good tuner with a clock that can perform both manual channel selection and time setting in one device.

[Brief explanation of the drawing]

FIG. 1 is a block diaphragm showing an example of the basic configuration of a tuner with a clock according to the present invention, FIG. 2 is a schematic front view of the tuner face of the tuner of a tuned frequency display, and FIG.
The figure is a schematic front view of the panel surface of the tuner when the time is displayed. 11...Tuner input circuit, 12...
Clock input circuit, 13...First switching circuit, 14
, 15, 16, 17...Circuit for obtaining digital output for frequency display or clock display, 18...
・First manual up circuit, 18'...First manual up switch, 19...Second
manual down circuit, 19'... second manual down switch, 20... second switching circuit, 21... second manual up circuit,
21'...Second manual attachment switch,
22...Second manual down circuit, 22'
...Second manual down switch, 30.
...Display unit, 31...Tuner panel.

Claims (1)

[Claims] 1 A circuit for obtaining a tuned frequency digital output for the tuner function and a clock digital output for the clock function, a switching circuit for switching the operation of this circuit for the tuner function and the clock function, and a circuit for the operation of this switching circuit. Therefore, it is equipped with a digital display that selectively displays the number of circuit boards and a digital clock, and an up-down device that controls increasing or decreasing the number of a predetermined digit on the digital display of this display. A tuner with a clock, characterized in that the device can be used for both manual channel selection using the tuner function and time setting using the clock function.