JPS5910591B2 - Method of manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a manufacturing method that can easily realize a structure of a field effect transistor with improved frequency characteristics.

Conventionally, an element having the structure shown in FIG. 1 has been proposed as a structure suitable for high frequency use of a vertical field effect transistor.

In the drawing, 1 is a semiconductor substrate with a high impurity concentration that becomes a drain region, 2 is a low impurity concentration semiconductor layer with a higher resistivity than the substrate 1, 3 is a control electrode layer called a gate region and is of the opposite conductivity type to the substrate 1, and 4 is a control electrode layer of the opposite conductivity type to the substrate 1. A source region is a high impurity concentration region of the same conductivity type as the substrate 1, 5 is an oxide film, and 6 is a metallized layer provided with an electrode for communication from each region to the outside. The basic structure shown in Figure 1 is called a surface wiring gate structure because the gate 3 is exposed on one main surface and electrode metal is wired on the exposed surface part to reduce gate resistance. It is. This surface wiring gate structure is
Unlike the buried gate structure of FIG. 2, which is normally used as a vertical structure, the distance between the gate and drain is long, and the distance between gate and source is short.

Further, when it is desired to make the electric field action by the gate sufficiently effective, it is common to form the gate sufficiently deep from the surface by a method such as diffusion. The disadvantage of the structures shown in FIGS. 1 and 2 is that in order to obtain triode characteristics in a vertical field effect transistor, the distance between adjacent gates must be made small or the specific resistance of the channel must be made sufficiently high. It is necessary to realize a state in which the channel portion between adjacent gates is depleted (pinch-off state) or a state close to it without applying an electric field to the gates.

At this time, the two methods of reducing the gate interval without increasing the specific resistance of the channel portion, or making the channel portion high in specific resistance, give similar results. In either case, the series resistance (
channel resistance or drain resistance) increases, making it difficult for current to flow.

On the other hand, since the capacitance between the gate and the drain is the capacitance of a parallel plate structure, it is proportional to the reciprocal of the thickness of the depletion layer extending from the gate to the drain side, and proportional to the area of the gate portion. This gate-drain capacitance Cdg also creates a path that is fed back to the input side as a negative feedback capacitance of the element, leading to a decrease in gain and high-frequency characteristics. The higher the resistivity of the semiconductor layer 2 between the gate and drain is, the easier the depletion layer is to expand, and the higher the resistivity is, the lower the capacitance is from a low voltage bias. However, if a high resistivity layer is used to reduce the capacitance, the channel resistance will increase.

If an attempt is made to improve the high frequency characteristics in this way, the channel resistance will increase, making it difficult for current to flow and reducing the output, making it difficult to achieve high frequencies and high output. A structure shown in FIG. 3 has been proposed as a means to solve the above-mentioned drawbacks. A feature of this structure is that a highly doped layer protrudes from a position of the drain region 1 facing the source region 4 along the shape of the depletion layer extending from the gate 3. According to this structure, the capacitance between the gate and drain is not large,
This has the advantage of reducing channel resistance. Furthermore, the breakdown voltage between the gate and drain does not change because it does not affect the extension of the depletion layer. Although the structure has such excellent features, it is extremely difficult to manufacture.

As a high-frequency element, the gate area is small and the distance between adjacent gates is also small to create a mutual conductor. When the capacitance is increased, the distance between adjacent gates becomes several micrometers, and it becomes extremely difficult to provide a protrusion of about 1 to 2 micrometers between the adjacent gates.

Conventionally, as a method for realizing such a structure, a predetermined surface area of the substrate 1 is selectively excavated in advance to form a concave portion, and then a semiconductor layer 2 is grown in a vapor phase on the substrate 1 in which the concave portion has been formed. The gate region 3 is formed in the surface layer of the semiconductor layer 2 onto which the recessed portion is projected, and the source region 4 is formed in the surface layer of the semiconductor layer 2 onto which the surface region of the substrate 1 other than the recessed portion is projected. However, there is a problem with controlling the excavation of the substrate 1, and a recess is also formed in the semiconductor layer 2, making photolithography for forming the gate region 3 and source region 4 difficult. There were extremely difficult manufacturing technology problems. This invention was made in view of these points, and is a gate. It is an object of the present invention to provide a manufacturing method that can easily realize a field effect transistor having a structure in which the drain resistance is reduced without increasing the capacitance between the drains and high output is possible.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a cross-sectional view of a main part of a field effect transistor manufactured according to an embodiment of the present invention. Formed by phase growth method.

Next, a mask layer for forming a gate region is provided on one main surface of the semiconductor layer 2 by a well-known method. After forming the gate region 3 using this mask layer as a mask, an impurity having an extremely high diffusion rate and having a conductivity type opposite to that of the substrate 1 is introduced at a low concentration almost equal to the impurity concentration of the semiconductor layer 2 using the mask layer as a mask. do. Thereafter, the source region 4 is formed by a normal method, for example, a thermal diffusion method. Then, during this process, the impurity with an extremely high diffusion rate diffuses as shown by the dotted line in FIG. 4, and forms the high resistivity region 2.
1 is formed. Here, as the impurity with an extremely high diffusion rate, an impurity with a diffusion rate higher than that of an impurity for forming a gate region is selected. For example, for an n-channel element, a P-type impurity such as aluminum, gallium, boron, etc. Therefore, an impurity such as boron having a low diffusion rate can be selected for forming the gate region, and an impurity such as aluminum can be selected as the impurity to be diffused to the channel region. However, these impurity groups are not limited to Group I elements, but can also be selected from Group I and Group elements. Also, Li, Au, Cu, Fe, Ni, Mn, CO,
It is also possible to use heavy metal elements such as Ti. These impurities, which alone do not cause conductivity in a semiconductor,
Since it acts as a carrier trap in semiconductors, it is advantageous that both n-type and p-type semiconductors have high specific resistance and generally diffuse at high speed. Furthermore, since these metal elements have a high diffusion rate, they have the advantage that they can be diffused from the gate portion for a short time after the completion of the diffusion process of the element. Note that it is desirable that the high specific resistance region 21 be formed as shown by the dotted line in FIG. That is, the adjacent high resistivity region 2
It is desirable to choose impurities that diffuse rapidly so that the 1's are continuous with each other. In the high resistivity region 21 formed in this manner, the depletion layer is easily extended, and an element with good characteristics can be realized. FIG. 5 is a cross-sectional view showing a lateral field effect transistor having a surface wiring structure manufactured by the method of the present invention, and is manufactured by the same method as that shown in FIG.

FIG. 6 is a sectional view showing a vertical field effect transistor having a buried gate structure manufactured by the method of the present invention, and specifically manufactured as follows.

First, the first n-type semiconductor layer 22 is formed on one main surface of the n+-type semiconductor substrate 1 by vapor phase growth. Next, a mask layer for forming a gate region is provided on one main surface of the first semiconductor layer 22. Then, using this mask layer as a mask, impurities for forming the gate region and impurities to be diffused to the channel region as described above are mixed and introduced.
Region 3 is formed. Next, after removing the mask layer, a second layer is formed on the first n-type semiconductor layer 22 including the P+ region 3.
An n-type semiconductor layer 23 is formed. Thereafter, when the source region 4 is formed by a well-known method such as a thermal diffusion method, impurities with a high diffusion rate are transferred from the P+ region 3 to the first and second regions.
is diffused into the n-type semiconductor layers 22 and 23 to form a high resistivity region 21. In the embodiment shown in FIG. 4 described above, the impurity with a high diffusion rate was introduced after the gate region 3 was formed. may be formed.

Furthermore, although the above description has been made by taking the manufacture of an n-channel device as an example, it goes without saying that the present invention can also be applied to the manufacture of a p-channel device.

As described above, according to the method of the present invention, a high output field effect transistor with excellent frequency characteristics can be easily obtained using a simple method.

[Brief explanation of the drawing]

FIGS. 1 and 2 are sectional views showing a conventional field effect transistor, FIG. 3 is a sectional view showing a field effect transistor with an improved structure, and FIGS. 4 to 6 are sectional views showing the method of the present invention, respectively. FIG. 2 is a cross-sectional view showing a field effect transistor thus manufactured. In the figure, 1 is a semiconductor substrate, 2 is a semiconductor layer, 3 is a gate region, 4 is a source region, and 21 is a high resistivity region.

Claims (1)

[Claims] 1. A step of forming a semiconductor layer of the same conductivity type as the substrate on one main surface of a low resistivity semiconductor substrate to be a drain region, and a step of forming a gate region on one main surface of the semiconductor layer. A step of providing a mask layer, using the mask layer as a mask, adding an impurity in the semiconductor layer to form a gate region having a conductivity type opposite to that of the semiconductor layer, and an impurity that has a higher diffusion rate than the impurity and increases the resistivity of the semiconductor layer. and forming a low resistivity source region of the same conductivity type as the semiconductor layer in the semiconductor layer. 2. The method of manufacturing a field effect transistor according to claim 1, wherein the impurity that increases the resistivity of the semiconductor layer is an impurity of a conductivity type opposite to that of the semiconductor layer. 3. The method for manufacturing a field effect transistor according to claim 2, wherein the impurity concentration is selected to be approximately equal to the impurity concentration of the semiconductor layer.