JPS5910615B2 - logic gate circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a saturated bipolar logic circuit, especially <TTL
( }Regarding improvement of input voltage vs. output voltage characteristics (input/output transfer characteristics).

FIG. 1 is a typical example of a conventional TTL.

1 is an input terminal section, 2 is a multi-emitter gate transistor, 5 is an emitter follower transistor, 7 is an inverter transistor, 9 is an output buffer transistor, 11 is a "1" level output transistor connected to transistor 9 in Darlington. configure the output buffer circuit.

12 is a power supply terminal, 13 is an output terminal, and 3, 4, 6, 8 and 10 are resistors.

As is well known, the input/output transfer characteristics of such a TTL are as shown in FIG.

In other words, the input voltage Vr increases (VBE5-VCE1
), the emitter follower transistor 5 enters the active state and the output voltage vo begins to drop, and after this the input voltage V1 further increases (VBE5+VBE7-, ■cE
1), inverter transistor 7 enters the active state, Vo decreases rapidly, and finally transistors 5 and 7
reaches saturation and settles to a low level output voltage.

However, VBE5 and VBE7 indicate the base-emitter forward voltage necessary for transistors 5 and 7 to start operating, respectively, and VCE indicates the collector-emitter voltage of transistor 1 in the active state.

As explained above, in the conventional circuit, the shoulders of the input/output transfer characteristics are rounded.

This reduces the maximum allowable input voltage required to guarantee the high-level output voltage required for the logic circuit, and thus reduces the logic circuit's low-level noise margin. means.

The present invention aims to provide new means to improve this drawback.

FIG. 3 shows an embodiment of the present invention, and the difference from the conventional circuit shown in FIG. 1 is that the emitter of the output buffer transistor 9 constituting the output buffer circuit and the
A shunt circuit consisting of a diode 14 and a resistor 8' connected in series is connected from the junction point of the base of the level output transistor 11 to the base of the inverter transistor 7.

Next, the operation of the TTL of the present invention will be described.

Now one of the input terminals is in positive logic.”
When the 0'' level is applied, the current flowing through the resistor 3 passes between the base and emitter of the transistor 2 and almost flows to the input side, so no base current is supplied to the transistor 5, and the transistors 5 and 7 are cut off. 9 and 11 become conductive, and output V.

By closing, "1" level is obtained.

Therefore, from the emitter side of transistor 9, diode 1
4. Current flows through resistor 8' and resistor 6, so
A certain potential is applied to the base of transistor 7.

The forward base-emitter voltage vBE (for example, 0.6
volts) slightly lower (for example, 0.4 volts).

Also, when a "1" level is applied to all input terminals, the base-collector of transistor 2 becomes forward, transistor 5 becomes conductive, current flows through resistor 6, and transistor 7 is driven, so the output V.

becomes the "0" level. Next, we will discuss the input/output transfer characteristics.

For simplicity, it is assumed that voltage vI is applied to all input terminals.

While v■ is low, transistors 5 and 7 are in a cutoff state, so the output is approximately V.

Given by 0-2VBE.

Here. VCC is a power supply voltage.

vI gradually begins to increase (vBE5 - vCEI)
Then, in the conventional circuit, transistor 5 operates and the output voltage begins to decrease.

On the other hand, in the circuit of the present invention, when the input voltage is low and the transistor 5 is cut off, the resistor 4 and the transistor 9
, the voltage determined by the product of the current passing through the diode 14 and the resistor 8' and the resistor 6 is applied to the base of the transistor 7, so even if the input voltage V becomes (VBE5-vcE1), the output voltage does not decrease.

In other words, if the base potential of transistor 7 is set to, for example, 0.4 volts when transistor 5 is cut off, the output potential will remain unchanged until the input reaches a potential equal to (vBE5=VCE1) plus 0.4 volts. However, the low-level noise margin is significantly improved.

FIG. 4 shows an example of the input/output characteristics of the TTL of the present invention.

In the above embodiment, the diode 14 and the resistor 8' are all connected in series to form a shunt circuit, but it is clear that this could also be formed using only a plurality of series-connected diodes or only a resistor.

It is also possible to construct a shunt circuit by using a Marchemitter transistor as the transistor 11 and using a diode between its pace and emitter.

Additionally, regarding the role of the diode 14, it prevents part of the emitter current of the transistor 5 from being shunted to the base of the transistor 11 through the resistor 8' when the transistor 5 changes from the cut-off state to the active state. be.

Such a shunt causes problems such as an increase in the turn-on time of the transistor 7 and an increase in the total current of the circuit.

According to the present invention, it is possible to obtain a TTL which has almost the same number of elements as the conventional TTL, and which has a high input voltage at which the output voltage begins to decrease, and which has significantly improved low-level noise margin.

In the above description, a case has been described in which a two-transistor Turlington circuit is used as the output buffer circuit.

The present invention is a “0” level output transistor (inverter).
The method of applying the base potential of the "1" level output transistor and the base of the "0" level output transistor is characterized by the total resistance or diode,
Or by connecting via both, “1
``Since it improves the roundness of the shoulder in the TTL input/output transfer characteristic curve while maintaining the discharging function of the accumulated charge of the level output transistor, it can be used in other TTL circuits.

FIG. 5 is one example of this, in which the present invention is implemented in a so-called totem pole type TTL.

Since it is the same as that shown in FIG. 3 except that the output buffer circuit is composed of an output buffer transistor 9 and a diode 11', detailed explanation will be omitted.

The circuit shown in FIG. 6 is a conventional TTL having almost the same input/output characteristics as the present invention, but compared to the circuit shown in FIG. 1, it requires one transistor 16 and one resistor 15, so the circuit configuration is When the number of elements increases and the circuit is integrated, the chip area inevitably increases.

On the other hand, the present invention is suitable for integration because the chip area can be approximately the same as that of the circuit shown in FIG.

Although an example in which a multimitsuta transistor is used as an input gate has been described above, it is clear that the present invention can be applied to a NAND gate circuit using ordinary transistors or diodes, or an inverter circuit having one input terminal.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing a typical example of a conventional TTL, Fig. 2 is a diagram showing input/output transfer characteristics of a conventional TTL, and Fig. 3 is an example of an embodiment of the TTL of the present invention. The circuit diagram shown in FIG. 4 is the present invention T.
A diagram showing the input/output transfer characteristics of the TL, FIG. 5 is the TT of the present invention.
FIG. 6 is a circuit diagram showing another example of the conventional TTL. 1...Input terminal, 2...Input gate
Transistor, 3, 4, 6, 8, 8', 8//, 1
5... Resistor, 5... Emitter hollow transistor, 7... Inverter transistor, 9... Output buffer transistor, 11...
..."1" level output transistor, 12...
...Power terminal, 13...Output terminal, 11',
14...diode, 16...transistor.

Claims (1)

[Claims] 1. An amplification transistor with an emitter follower connection is inserted between an input gate circuit consisting of a diode or a transistor and an inverter transistor with a grounded emitter connection, and a base is inserted between the collector of the amplification transistor and the collector of the inverter transistor. In the logic gate circuit, an output buffer circuit including output buffer transistors each having an emitter connected to an output terminal via a P-N junction is inserted in the collector of the amplification transistor, wherein the emitter of the output buffer transistor is connected to the collector of the amplification transistor. and a base of the inverter transistor, a resistor or a series connection circuit of a resistor and a diode is connected in a forward direction when viewed from the emitter of the output buffer transistor to supply a bias potential to the base of the inverter transistor. logic gate circuit.