JPS5911283B2 - Video intermediate frequency signal synchronous detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video intermediate frequency signal synchronous detection circuit that improves the tank response characteristic of a video intermediate frequency detection circuit of a television receiver.

FIG. 1 shows an example of a wiring diagram of a conventional semiconductor integrated synchronous detection circuit used in a video intermediate frequency signal detection circuit of a television receiver.

In the figure, reference numerals 1 and 2 are input stage transistors which receive a video intermediate frequency signal (hereinafter referred to as IF10 signal) modulated by a video signal, chroma signal, or audio signal. 3 and 4 are first differential amplifiers that amplify this VI; 5 and 6 are coils and capacitors that are connected to the collector of this first differential amplifier and form a tuned circuit that extracts the carrier wave;
7 and 8 are diode diodes connected in parallel to this tuning circuit and in opposite phases to each other; 9 and 10 are transistors that send out a switching signal generated from the carrier wave extracted above;
1 and 12 are second differential amplifiers that amplify the VIF, 1
3 and 14, 15 and 16 are third and fourth differential amplifiers connected in cascode to this second differential amplifier, 51 is a VIF signal input terminal, 52 is a detection signal output terminal, 53,
54 is a power supply terminal, and 55 to 58 are constant current sources.

The conventional VIF signal synchronous detection circuit is configured as described above, and the input from the VIF signal input terminal 51 is amplified by the input transistors 251 and 2 (in the example shown in FIG. 1, this transistor is used as a single-ended transistor). (in this case, the bias circuit is omitted), the signal is sent to the first differential amplifiers 3, 4 and the second differential amplifiers 11, 12. The first differential amplifier 3, 4 has a tuned circuit 5 connected to the collector 30;
6 extracts the carrier frequency of the VIF signal and connects the diode T
, 8 and output transistors 9 and 10 form a switching signal from the carrier frequency and output it. The third differential amplifiers 13, 14 and the fourth differential amplifiers 15, 16 are double-equalized differential amplifiers, and each base receives a switching signal and the emitter receives a VIF signal. The signal is synchronously detected and its output is taken out from the output terminal 52.
In the circuit configured as above, the VIF signal input terminal 51
If the same amount of phase delay occurs with respect to the VIF signal in the path from The relative phase difference between the switching signal applied to each pace of the double-balanced differential amplifiers 13 to 16 and the VIF signal applied to each of their emitters is determined by the tuning frequency of the tuned circuit formed by the coil 5 and capacitor 6 of VIF. When the frequencies match, it becomes zero, and when the VIF frequencies deviate, only the phase difference δ corresponding to the deviation becomes.

In this case, if the VIF signal is i(t)COswt, the phase of the switching signal Vs will be (Wt-δ).

Since the synchronous detection output VO is the product of the switching signal and the VIF signal, VOaVi(t)COswtxcOs(Wt
-δ)...゛...(1), and if the high frequency (2w) component is omitted, it becomes VOαi(t)COsδ. In this case, since δ is in the range -90i<δ +900, the polarity of VO will not be reversed. However, in the conventional synchronous detection circuit shown in FIG. VI
If more phase delay is caused with respect to the F signal and the difference is expressed as θ, the phase of the switching signal s' is (Wt - δ - θ)
Then, the synchronous detection signal output v♂ at that time is VO″αVi
(t)COs(δ+θ) (4) Since δ is a function of frequency, the response characteristic showing the relationship between the detection output VO and frequency is as shown in FIG. 2, for example.

The characteristics shown in FIG. 2 are determined by the tuning circuits 5 and 6, and are therefore called tank response characteristics. In tank response characteristics, the variation range of δ is limited to -900 to +96°, but the variation range of δ + θ exceeds the above range in the direction where δ has the same polarity as θ, so there is a part where the polarity of V♂ is reversed. (section B in Figure 2) may occur, and as a result, the image may be reversed. The object of the present invention is to obtain a video intermediate frequency signal synchronous detection circuit in which the phase difference θ between the switching signal and the detected IF signal becomes zero, and abnormal phenomena such as video inversion as described above do not occur. It is something to do.

FIG. 3 is a wiring diagram showing one embodiment of the present invention.
16, 51 to 58 are exactly the same as the above-mentioned conventional device.

Blocks 40 and 41 surrounded by dotted lines are the blocks 40 and 41 of the second differential amplifier 1.
The phase shift circuit provided at the inputs of 1 and 12, 42 and 43 are transistors for this phase shift circuit, 44 and 45 are base resistors of this transistor, and 46 and 47 are emitter resistors for the above phase shift circuit. . There are various causes for the above-mentioned phase difference, and one possible cause is the difference between the circuit path until the switching signal is formed and the circuit in which the VIF signal is detected.

FIG. 4 shows the results of experimental measurements of how much phase delay occurs in the emitter follower transistor.

The horizontal axis represents the output impedance of the signal source applied to the base of the emitter follower transistor, and the vertical axis represents the phase delay. The signal frequency in this case is 58.75MH
The emitter current at z is 1 mA. It can be seen from FIG. 4 that as the output impedance of the signal source increases, the phase delay also increases.

In the circuit of FIG. 3, what corresponds to the signal source output impedance is the impedance seen from the bases of transistors 9 and 10 to the switching signal shaping stage.
If a phase shift circuit corresponding to the phase delay caused by the emitter follower transistor is inserted on the VIF signal side, the phase difference can be made zero and the tank response characteristic can be improved.
For this purpose a second differential amplifier 11 of the VIF signal circuit
, 12 are inserted into the input sides of the phase shifters 40 and 41. The phase shifters 40 and 41 are composed of transistors 42 and 43, pace resistors 44 and 45, and emitter resistors 46 and 47.
The emitter follower circuit is configured as one emitter follower circuit, and the signal source output impedance is pace resistors 44 and 45.
In this way, a portion of the IF signal is transferred to transistors 1 and 2.
After a phase delay φ1 is generated by the phase shifters 40 and 41 from the emitter of On the other hand, a part of the VIF signal is amplified by the first differential amplifiers 3 and 4, and a switch signal is extracted and formed by the tuning circuits 5 and 6 and diodes 7 and 8.
It is added to double balanced differential amplifiers 13-16.

Assuming that the phase delay during this period is φ2, the phase shifters 40 and 41 have been adjusted so that φ1 and φ2 are equal, so the synchronous detection signal output o is expressed by equation (2), which is expressed as the frequency As shown in FIG. 5, there is no inversion, resulting in improved tank response characteristics. As explained above, the present invention has the effect of improving tank response characteristics and obtaining stable synchronous detection output without reversal phenomenon through the simple structure of inserting a phase shifter consisting of a base resistor and an emitter follower circuit.

[Brief explanation of the drawing]

Fig. 1 is a wiring diagram showing an example of a conventional video intermediate frequency signal synchronous detection circuit, Fig. 2 is a tank response characteristic diagram in the above circuit, and Fig. 3 is a wiring diagram showing an embodiment of the present invention.
FIG. 4 is a graph showing the phase delay in the emitter follower circuit, and FIG. 5 is a tank response characteristic diagram in the circuit of the present invention.

Claims (1)

[Scope of Claims] 1. A first differential amplifier that amplifies a video intermediate frequency signal and extracts a carrier wave using a tuning circuit, a switching signal generation circuit that generates a switching signal for synchronous detection using the extracted carrier wave, and the video intermediate frequency signal. a second amplifying the frequency signal;
A double-balanced differential amplifier consisting of a differential amplifier, a phase shift circuit inserted in the circuit of the second differential amplifier, and third and fourth differential amplifiers connected in cascode to the second differential amplifier. A video intermediate frequency signal synchronous detection circuit comprising a differential amplifier and a synchronous detection circuit for synchronously detecting the video intermediate frequency signal by adding the switching signal to the double balanced differential amplifier. 2 The phase shift circuit inserted into the circuit of the second differential amplifier is connected to an emitter follower circuit for video signal amplification provided on the input side of the second differential amplifier and the base of the transistor of the emitter follower circuit. 2. The video intermediate frequency signal synchronous detection circuit according to claim 1, wherein the output of the emitter follower circuit is connected to the input of the second differential amplifier. .