JPS5911286B2 - transistor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a transistor circuit called a current mirror circuit.

First, a conventional transistor circuit of this type will be explained with reference to FIG.

First and second PNP transistors Qt with equal characteristics
, Q2 are connected to a positive power source 1B, their respective bases are commonly connected to the collector of the first transistor Q1, and the first and second transistors Qt, Q2
First and second terminals T1 and T2 are led out from the respective collectors, and substantially equal currents flow through the first and second terminals T1 and T2.

Note that the first transistor Q1 functions as a diode.

Next, let us explain the operation of this transistor circuit.

The emitter and base currents of transistors Ql and Q2 are respectively Iol TS■E2;■B1 9■B2, and the currents of terminals T1 and T2 are 11t'2tl'
, Q2's emitter grounding current amplification factors are both hFE1
and each.

■El-IBI, so ■1 is expressed as the following equation.

■-I81+■B2 ・・・・・・・・・(1)1 Moreover, IB2 is expressed as in the following formula.

Moreover, I2 is expressed as in the following formula.

Transistor Q. , Q2 have the same characteristics and the voltages between both bases and emitters are equal, so IE1=
It becomes IE2.

Therefore: I2/I1 is expressed as follows.

Therefore, the larger hFE is, the closer I2/1 is to 1.

However, since there is a limit to the value of hFE, there is a limit to how close 12/■1 can be to 1.

Therefore, a transistor circuit of this type has been proposed in which the ratio 2/I1 is made closer to 11 as shown in FIG.

This will be explained below, but the same reference numerals are given to the parts in FIG. 2 that correspond to those in FIG. 1, and redundant explanation will be omitted.

In the transistor circuit of FIG. 2, in addition to the first and second transistors Q1 and Q2, a third NPN transistor Q3 is provided, and the first and second transistors Q3 are provided.
1, the base of Q20 is connected to the emitter of the third transistor Q3, the collector of the third transistor Q3 is grounded, and its base is connected to the emitter of the third transistor Q3.
1 collector.

Next, let us explain the operation of this transistor circuit.

The base current of the third transistor Q3 is IB3, and the common emitter current amplification factor is hFE2.

(1) 1 is expressed as in the following equation.

Moreover, ■B3 is expressed as in the following equation.

Moreover, (2) is expressed as in the following equation.

Transistor Q. , Q3 have the same characteristics and the voltages between both bases and emitters are made equal, so IE1-IE2 is obtained as in FIG.

Therefore, 2/I1 is expressed as follows.

Therefore, when comparing equations (4) and (8), both h F
When E, are equal, formula (8) is better than formula (4),
It can be seen that I2/I1 becomes closer to 1, but it is still insufficient.

When converting the transistor circuit shown in FIG. 2 above into a monolithic semiconductor integrated circuit, the first and second transistors Q+ and Q2 are lateral transistors, and the third transistor Q3 has its collector grounded, so it is a vertical transistor. It can be configured as

Therefore, in this case, hFEt thFE2 is 5,
Since it is about 40, ■2/I1 becomes.

Furthermore, by providing two or more second transistors Q2 (having the same characteristics) in FIGS. 1 and 2 and connecting them in the same manner, each of the plurality of second transistors Approximately equal currents can be made to flow from the two terminals.

FIG. 3 shows a case where, for example, three second transistors, ie, transistors Q2 and Q2' are provided.

T2, T2' are the respective transistors Q21Q2'
The second terminal is connected to the collector of the terminal.

In this case, by connecting current feedback emitter resistors RE1, RE2 tR'E2 with the same resistance value to the emitters 1 of each transistor Q1, Q2, Q2', this transistor circuit has a high S/N, low distortion, A wide dynamic range and high stability can be achieved.

However, when such a transistor circuit is made into a monolithic semiconductor integrated circuit, the resistors RE+RE2, R
A variation (for example, about a factor of 6) occurs in the resistance value of 'E2, and therefore a variation occurs in the currents (1), (2), and (I'2) flowing through the terminals T, tT2tT'2.

In view of these points, the present invention provides a transistor circuit of this type including a plurality of second transistors, which has high S/N, low distortion, wide dynamic range, and high stability. The aim is to obtain a high degree of equality of currents at a plurality of terminals.

In the transistor circuit of the present invention, the first terminal and N(
-2, 3, 4,...) second terminals, the collector and base of which are connected, the collector of the first transistor is connected to the first terminal, and the emitter of the first transistor is connected to the first terminal. are connected to the reference potential point through the first emitter resistor, and the other ends of N second emitter resistors each having one end connected to the reference potential point are connected to the same number of MN (M=i,
2, 3,...) second transistors (transistors of the same conductivity type as the first transistor)
The collectors of the two second transistors are connected in common to the emitters of the two second transistors such that a current approximately equal to the average current flowing through the N second emitter resistors flows through the N second terminals. distributedly connected to N second terminals,
The bases of the first transistor and the MN2 second transistors are connected to each other.

An embodiment of the transistor circuit of the present invention will be described below with reference to FIG. 4. In FIG. 4, parts corresponding to those in FIGS. Omit duplicate explanations.

In this case, the second transistor Q2 tQ in FIG.
Transistors (PNP type) Q2a, Q2b; Q'2a, Q'2b having the same characteristics are provided corresponding to '2.

A second emitter resistor i5R common to each emitter of transistors Q2 a t Q2 b.

2 to the power supply 1B, and the transistor Q'2 a
! Each emitter of Q'2 b is connected to a common second resistor R.
'E2 to the power supply 1B.

The collectors of transistors Q2a and Q'2a are connected to terminal T2, and the collectors of transistors Q2b and Q'2b are connected to terminal T'2.

In this case, the emitter resistance h RE 2 , R' E 2
Let I and I'E2 be the currents (DC currents) flowing in the transistors, and if the base currents of the transistors Q2a, E2 Q2 b, Q'2 a t Q'2 1) are ignored, the current I2tI'2p is as follows.

The transistor circuit shown in FIG. 4 can be used, for example, as an active load in an amplifier circuit, a multiplication circuit, etc.

In the case of Fig. 4, each transistor Q1 tQ 2a
t Q 2b t Q'2 a t Q'2
b * In the case where Q 3 is PNP type, NP
In the case of N type, it can be configured as shown in Figure 5, but
In FIG. 5, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and redundant explanation will be omitted.

In the case of Fig. 4, the reference potential point was the power supply 1B, but
In the case of Figure 5, it is grounded.

The transistor circuit shown in FIG. 5 can be used as a constant current circuit of a differential circuit.

Next, an example in which the transistor circuit of the present invention is applied to a stereo demodulation circuit will be explained with reference to FIG.

In Fig. 6, 1 is an input terminal to which a composite stereo signal is supplied, 2a and 2b are input terminals to which a 38kHz subcarrier signal is supplied, and 3L and 3R are left and right audio signal output terminals which are stereo demodulation outputs. It is.

Also, 4 is the power supply terminal, and this is the power supply +B? Connected.

6 and 7 are first and second differential amplification circuits (first and second transistor circuits) to which composite stereo signals are supplied, respectively.

10 consists of third and fourth differential amplification circuits (differential switching circuits) 8 and 9, to which the subcarrier signal and the composite stereo signal from the first differential amplification circuit 6 are supplied and multiplied. It is a multiplication circuit.

23 is a current mirror circuit.

The first differential amplifier circuit 6 includes amplifier transistors Tr, , T
r2, constant current transistor T r3 a +Tr3d
It is composed of 1Tr6a to Tr6d.

The respective emitters of the transistors Trl tTr2 are connected to each other through a resistor 36 for linearity improvement.

Each emitter of transistors Tr3a-Trad is grounded through a resistor 43, and transistors Tr6a-Tr6
It is grounded through each emitter of d.

The second differential amplification circuit 7 includes an amplification transistor Tr4.
tTr5, constant current transistor Trl 7 aTr
It is composed of y 7d tTrt sa -Trx sd.

The respective emitters of transistors Tr4 to tTr5 are connected to each other through a resistor 37 for linearity improvement.

Each emitter of the transistors Tr1a-Tr,b is grounded through a resistor 45,
Each emitter of Tr r 8d is grounded through a resistor 46 .

Furthermore, the emitter of transistor Tr1 is transistor T.
raa wTr6b tTr+ 7d tTrt s
b is connected to each IL/ctor.

Emitter of transistor T,2 or transistor Tr3d
It is connected to each collector of wTraa tTr+ 7 c and Trl8C.

Emitter of transistor Tr4. Ball transistor Tr
3o,Tre e,'rr17 a t Trt s
d to each collector.

The emitter of transistor Tr5 is transistor Tr3
It is connected to each collector of b tTr6 d , Tr1 b , and Trl B2L.

Constant current transistor 'l'r3 a −jTr3 d tTr6a − of the first and second differential amplifier circuits 6 and 7
'rr6d ;Tr, . ,a −'rr I 7 d
tTrIB a--'rr1B d are NPN transistors with the same characteristics, and for these transistors, a muting control switch SW7, a resistor 30 and a transistor Trl are connected between the power supply terminal 4 and the ground.
Series circuit of 5 and resistor 42? A circuit is provided which includes a diode-configured transistor Trl6 connected between the collector and base of the transistor Trl5 and the transistor Trl5.

The base of the transistor T,15 is the transistor Trs
a-Trsd,T'r"6a-T'r6 d:Tr
, 7a-T, 17a tTrl 3a ~ Tr18d
are commonly connected to each base.

The resistance of the resistor 42 is made equal to that of the resistors 43, 44, 45, and 46.

And transistor Tr3a~'rr3a%'rr
a a~Tr'6 d;'rr, 7a~T"rt
7d %T'rt 8 a. ~TT18d and the resistors 42, 43, 44, 45, and 46 constitute a current mirror circuit 50, which is a transistor circuit according to the present invention.

In this case, the current flowing through the resistors 43 to 46 is ■.

1 to IO4 are equal.

As described above, the multiplication circuit 10 is composed of the third and fourth differential amplification circuits 8 and 9.

The third differential amplifier circuit 8 includes a pair of amplifier transistors Tr.
7, Tr8.

The fourth differential amplifier circuit 9 is an amplifier transistor T rg
, Ty10.

A subcarrier signal of 938 kHz is supplied to the third and fourth differential amplifier circuits 8 and 9 as balanced inputs from the input terminals 2a and 2b.

The multiplication circuit 10 is connected to the collector side of each amplification transistor Tr, Tr of the first differential amplification circuit 6 so as to be stacked thereon.

The collectors of the transistors Tr7 and Tr9 are connected to the power supply E3 through the load resistor 20, and the transistors T
The collectors of r8 and 'rrto are connected through a load resistor 21 to a power source E3.

These load resistors 20 and 21 have the same resistance value RL.

A left audio signal output terminal 3L is led out from each collector of the transistors Tr and Tr.
Right audio signal output terminal 3 from each collector of 8 and TrlO
R has been derived.

The current mirror circuit 23 is the third and fourth one of the multiplication circuit 10.
Transistors Tjll and T are stacked on the collector side of each transistor of the differential amplifier 11 circuits 8 and 9.
rl2 and the transistor T of the second differential amplifier circuit 7
Transistor Tr13 connected to the collector side of 'r+
tTrt4.

The collectors of the transistors T'r'y and Tr9 are connected to the transistor T'rtt-rector, and the emitter of the transistor Tl''l1 is connected to the current feedback emitter resistor ?38
It is connected to the power supply terminal 4 through.

Furthermore, the collectors of transistors T, 8 and Trxo are
It is connected to the collector of the transistor Tr1, and the emitter of the transistor Tri is connected to the power supply terminal 4 through a current feedback emitter resistor 39.

The collector of the transistor Tr4 is the transistor Tl"l
The emitter of the transistor Tr14 is connected to the power supply terminal 4 through the current feedback emitter resistor 40, the collector of the transistor Tr13 is grounded, and the emitter of the transistor T is connected to the base r3 of the transistor Tr4. and transistors T, 11 and Trl2
connected to each base.

In addition, resistors 39, 40. 41 is the same resistance.

In this way, the current based on the composite stereo signal flowing between the collector and emitter of transistor Trl4 is relayed to transistors T'rt and Tr1.

The bias power supply (
Constant voltage power supply) E2 connects resistors 1 with the same resistance value.
The same bias voltage is applied through 5, 16, 17 and 18.

Note that a resistor 41 is connected between the bases of the transistors T r1 5 T r4.

Then, when the composite stereo signal from the input terminal 1 is supplied to the base of the transistor Tr2 of the amplifier circuit 6, the composite stereo signal is passed through the separation control variable resistor 5 to the second differential amplifier. Width increasing circuit 7
The voltage is supplied to the base of the transistor Tr5.

Then, as in the past, a circuit (not shown) is provided that detects (amplitude detection) the intermediate frequency signal from the FM intermediate frequency amplification circuit and provides an output when the detected output is below a predetermined level. is used as a muting control signal to control the switch (actually, a semiconductor switching element) SW to turn it off during muting.

Next, the operation of the circuit shown in FIG. 6 will be explained with reference to the equivalent circuit shown in FIG.

In FIG. 7, parts corresponding to those in FIG. 6 are designated by the same reference numerals, and redundant explanation will be omitted.

In FIG. 7, 27 and 28 indicate current sources for the multiplication outputs (R-L) and (L-R) containing the DC current 2 from the multiplication circuit 10.

Further, 25 and 26 respectively indicate the main audio signal K in the composite stereo signal containing the DC current 1 from the second differential amplifier circuit 7.
(R+L) current source is shown.

K is a constant determined by the resistance of resistor 5.

Then, the left audio output obtained by adding the currents from the current sources 26 and 28 is obtained at the output terminal 3L, and the output terminal 3R
In this case, the right audio output is obtained by adding the currents from the current sources 25 and 27.

The gain of a differential amplifier circuit is determined by the product of mutual conductance and load resistance, and the mutual conductance depends on the constant current of the constant current circuit, and the smaller the constant current, the smaller the gain.

When the level of the received signal is sufficiently large, the switch SW is on and a predetermined DC current flows through each constant current transistor of the first and second differential amplifier circuits 6 and 7, and the amplifier circuits It operates normally, and stereo demodulated outputs, that is, left and right audio signals, are obtained from the output terminals 3L and 3R.

When the level of the received signal is below a predetermined level, the switch SW is turned off, the voltage of the power supply E1 becomes zero, and each constant current transistor of the first and second differential amplifier circuits 6 and 7 is cut off. , the current flowing through them becomes zero.

Therefore, the equal width amplifying circuit stops operating, and the output terminals 3L,
You will not be able to get a stereo demodulated output compared to 3R,
Muting is performed.

Also, by adjusting the separation control resistor 5, the composite nulleo signal supplied to the second differential amplification circuit 7, especially its main audio signal? The input level can be varied, allowing separation control.

In this case, the transistors Tr and T of the first and second differential amplifier circuits 6 and 7 are supplied with composite stereo signals, respectively.
Since the potentials of the bases of r5 are exactly the same, no direct current flows through the resistor 5, and therefore the stereo demodulation output terminal 3
The DC level of the L and 3R stereo demodulation outputs does not change.

According to the transistor circuit of the present invention described above, high S/N1
Along with low distortion, wide dynamic range, and high stability,
A transistor circuit in which the currents of the plurality of terminals for the plurality of second transistors are highly equal can be obtained.

Furthermore, according to the stereo demodulation circuit shown in FIG. 6 to which the present invention is applied, there is no difference in dynamic range between the left and right channel circuits, and noise generation due to offset during muting can be avoided. .

[Brief explanation of drawings]

FIGS. 1, 2, and 3 are circuit diagrams showing conventional transistor circuits, FIGS. 4 and 5 are circuit diagrams showing an embodiment of the present invention, and FIG. 6 is a stereo demodulation to which the present invention is applied. FIG. 1 is a circuit diagram showing an example of the circuit, and FIG. 1 is a circuit diagram showing an equivalent circuit thereof. T1 is the first terminal, T2 t T'2 is the second terminal,
Q1 first transistor, Q2a, Q2b, Q'2a
, Q'2b are second transistors, RE1 is a first emitter resistor, and RF,2, R'i2 is a second emitter resistor.

Claims (1)

[Claims] 1 First terminal and N (-2t3t4,...)
The collector of the first transistor is connected to the first terminal, and the emitter of the first transistor is connected to the reference potential point through the first emitter resistor. and the other ends of the N second emitter resistors, one end of which is connected to the reference potential point, are the same number of MN (M=1, 2, 3,...)
A current that is commonly connected to the emitters of the N second transistors (transistors of the same conductivity type as the first transistor) and is approximately equal to the average current of the currents flowing through the N second emitter resistors. The collectors of the two second transistors MN are connected in a distributed manner to the N second terminals such that MN flows to the N second terminals;
A transistor circuit characterized in that the bases of the transistor and the two second transistors of MN are connected to each other.