JPS5911289B2 - Automatic tuning device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic tuning and tuning device for a radio receiver having a built-in electronic storage means.

Conventional radio receivers, such as car radio receivers, have generally mechanically memorized the tuning position and then been able to tune in by simply pressing a switch.

However, in recent years, semiconductor memory elements have become small, lightweight, and available at low cost, and are now being used in the tuning circuits of radio receivers.

In other words, an automatic tuning selection circuit was devised and an integrated circuit developed specifically for this purpose, which allows you to tune into the stored station as many times as you like by simply pressing or touching the tuning switch once it has been memorized. Circuits have also become commercially available.

A first object of the present invention is to provide an automatic tuning selection device in which mechanical recording means is replaced with electronic storage means.

The second object of this invention is that once the information is stored in an electronic storage means, the tuning switch can be automatically swept by pressing or touching the tuning switch for a while, and when it is tuned to a predetermined frequency, the tuning switch can be automatically swept. An object of the present invention is to provide an automatic tuning tuning device that stops sweeping.

A third object of the present invention is to automatically sweep a conventional tuning device having an electronic storage device until it tunes a station by only momentarily pressing the button, which was previously pressed continuously during the sweep period. The purpose is to provide a control circuit that automatically stops the sweep when synchronized.

First of all, the known technology that forms the background of this invention will be explained.

FIG. 1 is a schematic circuit configuration diagram showing a conventional example of a tuning tuning device having a built-in manual memory.

1 is a tuning switch consisting of a keyboard switch or a touch switch (census inch) provided on the front panel of the radio receiver, and when the person listening to and operating the radio receiver operates this, the Channel selection command and memory built into the receiver (RAM = Randa)
m AccessMemory) 75.

The output of the tuning switch 1 is converted into a pinary code by an encoding stage 2 consisting of a diode matrix 78 and a latch circuit 79, for example.

The latch circuit 79 holds the pinary code indicating a predetermined frequency even if the operator releases the tuning switch 1.

Encoding stage 2 can be configured by combining diodes and transistors as described above, but for example, Texas Instruments' 16-pin NDual-in-Ii
The circuit configuration can be simplified by using an integrated circuit with the trade name SN29791N, which has an 8CH input sensor and a 4-pit binary output, which is housed in the ne Package.

The pinary code is applied to a sweep voltage generator 77 that supplies a sweep voltage to a tuner section 69 using a varactor diode.

Inside the sweep voltage generator 77 is a semiconductor memory IJ (RAM).
) 75, the pre-written voltage is read out according to the input pinary code, and sent to a tuner section 69 using a varactor diode to tune to a station having a selected predetermined frequency.

It also has a first control switch 19A for continuously changing the sweep voltage from high to low and from low to high only while the switch is pressed.

Tuning switch 1 is a plurality of tuning switches 11+12t1
-3, . . . 1-n, and can select or store n stations.

If you use the above-mentioned integrated circuit SN29791N, up to 8
Stations can be selected and stored.

That is, after momentarily pressing the tuning switch 1-, the first control switch 19A is operated only while being pressed and released, and when the sweep voltage is thereby stopped, the tuner section 6
The voltage applied to the varactor diode 9 is stored in the memory 75.

If the first control switch 19A is released to stop the sweep voltage at the same time as tuning to a station, that station is memorized.

Next, when one of the channel selection switches 1-2 is momentarily touched and the first control switch 19A is operated and stopped again, the frequency at that point (the station, if any) is stored.

Similarly, if you use SN29791N, you can store up to 8 stations.

From then on, simply by arbitrarily selecting and pressing the tuning switch 1, the stored tuning voltage of the station is read out and applied to the varactor diode of the tuner section 69.

Is Figure 2 shown in Figure 1? A specific circuit example of the tuning switch 1 and diode matrix 7B? show.

There are 20 channel selection switches 1 (1-1, 1-2,...
1-2o), and 20 frequencies (
or a station).

One electrode of the tuning switch 1 is commonly connected and connected to a positive DC voltage terminal 80. For example, when a finger touches 1-8 in the tuning switch 1, the tuning switch 1 closes; During the touching period t1, the code output terminals 20, 21, 22, 23, 8 pass through the diode matrix 78.
1 and 82, an output as shown in FIG. 3 appears.

In this case, t1 and +t2 are the periods during which the channel is selected, and t
33 indicates the period when the channels 1- and o in the channel selection switch 1 are closed next.

FIG. 4 is a specific circuit example of the latch circuit 79 in FIG. 1, which includes 10 NAND circuits N11t N12t-, N1
With the latch circuit configuration mainly consisting of 9 and N2o, the output of the diode matrix 18 shown in Fig. 2 is pinally coded as 2°, 2l, 22, 23, 24 at the five terminals A-E. The hold output is sent out as shown in FIG.

The switch positions that provide 20 frequencies are encoded by this pinary code, and with this encoded signal as input, the pre-stored tuning voltage for each frequency is read out and applied to the tuner section 69 for tuning. be done.

Next, the D-A conversion means 3 and the integration circuit 8, which are the constituent elements of the sweep voltage generation stage 77, will be explained.

The integrating circuit 8 integrates the rectangular wave appearing in the output of the DA converting means 3 with a constant period and varying duty cycle, and generates a voltage corresponding to the duty cycle.

FIG. 6 is a block diagram showing the basic circuit configuration of the DA converting means 3 of FIG. 1.

In this figure, 75 is a memory (RAM) called station memory consisting of random access memory, and A
-E converts the pinary code input on 5 lines into a 20-line signal, thereby storing the pre-written station voltage corresponding to each frequency or reading it out as an output.

The read output is given to a rectangular wave generator 83 consisting of a data comparator.

A clock pulse is applied to this rectangular wave generator 83 from the clock oscillator 5 via the clock input terminal 32 and the pinary counter 72, and this pulse is counted by the output of the memory (RAM) 75.

The output obtained from the rectangular wave generator 83 by the counting operation becomes a rectangular wave with a constant period and a duty cycle (fd=t/T) selected by the output of the memory 75, and the duty cycle (fd) is determined by the output of the memory 75. Alternatively, it is varied from 0 to 1 depending on the output of the program generator 76, but here, since there are 20 frequencies selected by the 20 channel selection switches 1, it is varied in 20 steps.

On the other hand, while the first control switch 19A is pressed so that the program generator 76 can be driven by the first control switch 19A and the program generator 76 can be written to and read from the memory 75, the presettable up-down counter 73 is set to a higher or lower value. By counting in the opposite direction, the duty cycle can be changed continuously from 0 to 1 and from 1 to O.

The program generator 76 operates using a clock pulse as a reference signal.

Next, an automatic tuning tuning device which is an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 7 is a circuit diagram of an embodiment of the present invention.

1 is a plurality of channel selection switches that generate temporary trigger signals, and is a switch that is turned on only while being pressed or a sensor switch group that is turned on only when touched; It also serves as a switch for

One end of this switch electrode is connected to ground the terminal commonly connected to each switch only when turned on.

The other end is the sensor input terminal 1B, 11, 12 of the encoding means 2.
, 13, 14, 15, 16, and 17.

20, 21, 22, and 23 are code output terminals, and as shown in FIG. 21, 22, and 23.

That is, 18 is the rLJ level, 11, 12, 13, 14, 1
When signals 5, 16, and 17 are all at the "H" level, the code output terminals 20, 21, and 22 are at the "L" level, and 23 is at the rHJ level tonal, as shown in FIG.

Although the encoding means 2 can be designed with a diode, a resistor, and a capacitor as described in the conventional example, in the embodiment of the present invention, the circuit is designed using an integrated circuit SN manufactured by Texas Instruments.
29791N is used to simplify the circuit design.

3 is a D-A conversion means, and it goes without saying that this circuit can be designed using resistors and capacitors like the encoding means 2, but in this embodiment, the integrated circuit SN76721N from Texas Instruments is used. An example of the circuit used is shown.

FIG. 9 shows the equalization circuit of SN76721N.

Since this is almost the same as the DA converting means 3 shown in FIG. 6, only the different points will be explained.

The data comparator 74 corresponds to the rectangular wave generator 83 in FIG.

The memory 75 is equipped with memory holding terminals 34 and 35, and as shown in FIG. The contents of the memory 75 are not erased when the power is turned off.

The rest is exactly the same as the 1,000-stage DA conversion 3 explained earlier.

6 is a buffer amplifier for amplifying the pulse width modulated signal output from the pulse width modulated output terminal 33, 7 is a DC amplifier for further amplifying the output of the buffer amplifier 6, and 8 is the output of the DC amplifier. This is an integration circuit for integrating .

The output of this integrating circuit 8 is applied to a tuner section 69 of a receiving device 68 shown in FIG.

The tuner section 69 uses a town variable capacitor as a tuning element.

A typical example is a varactor diode.

9 is a muting control circuit that suppresses unnecessary tuning sound (beat) that occurs when moving from a stored frequency to the next frequency; 54 is a muting control terminal for taking out a signal to the muting circuit 31; 24 indicates a muting terminal.

While a sweep voltage that successively increases or decreases is generated at the sweep output terminal 53, the muting output terminal 54
is kept at zero potential and is used as a voltage applied to the muting circuit 31 of the receiving device 6B.

10 is an AFC unlock circuit, and a sweep output terminal 53
While the sweep voltage is being taken out, the AF of the receiving device 68
This is to release the C circuit 71. During this time, the AFC unlock terminal 55 is kept at zero potential and is supplied to the AFC circuit 71 of the receiving device 68, and the AFC circuit 71 remains stationary during this time.

Next, the control circuit 57 connected to the rise control terminal 25 and the fall control terminal 26 will be explained.

Detailed circuit connections of this circuit are shown in FIG.

Control Lake H Catfish ζ 7L O D-^Na Fishing Area 2 rtr
1. A rise control switch 3 that operates the double pull-up down counter 73 in the upward direction or downward direction by applying a temporary trigger signal to the second control switch 19.
7 and a lowering control switch 3B, both switches 37
．． By applying a temporary trigger signal to the D-A conversion stage 3 by 38, the presetter pull up/down counter 73 is automatically counted up or down, thereby changing the duty cycle and outputting the signal to the sweep output terminal 53. A control that operates while supplying a sweep voltage that continuously changes from low to high or high to low receiving frequency, and automatically stops the sweep when the receiving device 68 is tuned to a certain station. It is also a preset circuit for storing the frequency at the stopped position in the memory 75.

The control circuit 57 mainly includes five switching elements Q1.
, Q2-Q3, Q4, Q5 switching circuit 39, 41, 40, 42, 51 and 4
NAND circuits N1, N2, N3? Consists of N4.

49 and 50 form a flip-flop, S is a set input terminal, R is a reset terminal, and Q, Q are output terminals.

The operation of the control circuit 57 will be explained with reference to the operation waveform diagram shown in FIG.

When both the rise control switch 37 and the fall control switch 38 of the second control switch 19 for operating the presetter pull-up/down counter 73 attached to the 1,000-stage D-A conversion 3 are in the OFF state. Since a positive DC voltage is applied to the input terminals X and Y of the NAND circuit 49 via the power supply terminal 56 through the resistors R1 and R7, X and Y are at the rHJ level.

The NAND circuit N3 has two input terminals connected to each other and operates as an inverse circuit.

On the other hand, a DC voltage is applied to the switching input terminal 52 from the detection section 70 of the receiving device 68 shown in FIG. 12 during tuning.

The detection unit 70 detects that the intermediate frequency amplification stage of the receiving device 68 is tuned by the tuning resonance characteristic, and generates a DC voltage.

When a DC voltage is generated at the switching input terminal of the switching circuit 52, the switching element Q5 of the switching circuit 51 is turned on, and the collector of the switching element, that is, the reset terminal R of the flip-flop circuit becomes "L" level.

Currently, no DC voltage is generated at the switching input terminal 52 because the switching input terminal 52 is not tuned.

Therefore, since the switching element Q is in the off state, the reset terminal R of the NAND circuit N1 is at the "H" level, and the output terminal 2 of the NAND circuit N4 is at the rLj level because the input terminals X and Y are at the "H" level. Since N3 is an inverse circuit, the set terminal S of the flip-flop consisting of NAND circuits N1 and N2 is at the rHJ level, so the output Q of the flip-flop is at the "L" level. Therefore, the bases of the switching element Q2 and the switching element Q4 are connected to the diode 45 and the diode. 46 is clamped to the rLJ level and becomes a cut-off state, and the rise control terminal and fall control terminals 25 and 26 of the 1,000-stage D-A conversion 3 connected to the collectors of the switching element Q2 and the switching element Q4 are at "H" level. is maintained.

At this time, the switching elements Ql and Q3 have resistors R
Since bias is supplied by Q2 and R8, it is in an on state, and both collectors of switching elements Q1 and Qs are at the "L" level.

Now in this state (1 = 0 to 1 in the operating waveform diagram shown in Figure 11)
= 1, up to), and the rise control switch 37 is turned on instantly (
12-11 hours) When pressed and released, NAND circuit N4
Since the X terminal of the switch is grounded to the ground via the rise control switch 37, it changes from the "H" level to the "L" level, and returns to the "H" level when the hand is released.

This situation is shown in the operational waveform diagram 58 in FIG.

Similarly, when the descending control switch 38 is pressed momentarily (16-14 hours) and released, the Y terminal of the NAND circuit 47 is grounded to the ground via the descending control switch 38 and changes from rHJ level to "L" level. When you release your hand, it returns to the "H" level again.

This situation is shown in the operational waveform diagram 59. At the Z terminal of the NAND circuit N4, a voltage having the waveform shown in the operating waveform diagram 60, which is the sum of the opposite polarities of the X and Y terminals, is generated.

That is, only when the ascending control switch 37 or descending control switch 38 is pressed (Δ1 = 12-11 - t6 - t4 hours) "
A trigger signal that changes from the "L" level to the "H" level is generated.

Since the NAND circuit N3 following the NAND circuit N4 operates as an inverse circuit as explained earlier, the output of the NAND circuit N3, that is, the set terminal S of the flip-flop has the opposite polarity of the operating waveform 60 (the operating waveform 60 is inverted). ) voltage of operating waveform 61 appears.

When the rise control switch 37 is pressed, the input terminal X of the NAND circuit N4 becomes "L" level, and the switching element Q
The base of t becomes the "L" level, and therefore the collector of the switching element Q1 transitions from the "L" level to the rHJ level.

Once it transitions to the "H" level, the DC feedback voltage is supplied to the switching element Q1 from the collector of the switching element Q2 through the resistor R5, so even if the rise control switch 3T is turned off, the collector of the switching element Q1 remains "
Maintain the "H" level.

Here, the diode 85 is for preventing backflow.

Here, when a DC voltage enters the switching input terminal 52, the switching element Q5 is turned on, and the reset input terminal R of the NAND circuit N1 transitions from the "H" level to the ILJ level, and the flip-flop consisting of the NAND circuit N and tN2 is activated. is inverted, and its output Q goes from rHJ level to “L”
level, the base of the switching element Q2 becomes "L" level through the diode 45, and the switching element Q2 enters the cut-off state.
The collector of is transferred from the rHJ level to the “L” level,
At the same time, the switching element Q1 is turned on, and the collector of the switching element Q changes from the "H" level to the "L" level, and operates as shown in the operation waveform diagrams 64 and 65.

However, if the rise control terminal 25 and the fall control terminal 26 are set to the rLJ level at the same time, that is, if both switches are pressed at the same time, the D-A conversion 1,000-stage 3 will become inoperable and will not return unless the power is turned off once, so the diode 43.44 By adding , when the down switch 38 is pressed while the switching element Q2 is on, the base of the switching element Q2 is grounded and turned off, and the switching element Q4 is turned on after a time constant (t=RtO - C2) consisting of the resistor RIO and the capacitor C2. The collector of switching element Q4 transitions from "H" level to "L" level and drops control terminal 2.
6 becomes the "L" level, the rise control and fall control terminals 25 and 26 will not become the rLJ level at the same time.

Note that if a seesaw type switch is used as the second control switch 19, the mechanism prevents buttons 25 and 26 from being pressed at the same time, and the above-mentioned defect can be avoided.

According to the configuration of 1F, the initial purpose can be achieved,
If this is applied to a car radio receiver, it will be easier to operate as it can automatically sweep and memorize with just a momentary press, compared to conventional systems where the listener cannot let go of the sweep. Therefore, it is very effective when driving a car.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit diagram showing a conventional example of a tuning device with a built-in manual memory, and FIG. 2 is a specific circuit diagram of the signal generation stage 1 and diode matrix 78 in FIG. 3 is an operation waveform diagram for explaining the circuit operation in FIG. 2, FIG. 4 is a specific circuit diagram of the latch circuit 79 in FIG. 1, and FIG. 5 is for explaining the circuit operation in FIG. 4. The operation waveform diagram of FIG. 6 is D-A in FIG.
A circuit configuration diagram showing the basic configuration of the 1,000-stage conversion 3, Fig. 7 is a circuit configuration diagram showing the automatic tuning device of a radio receiver to which the present invention is applied, and Fig. 8 shows the sensor input terminal and code output terminal. 9 is a configuration diagram of an integrated circuit that is one of the D-A conversion means 3, FIG. 10 is a detailed circuit connection diagram of the control circuit 57, and FIG. 11 shows the operation of FIG. 10. This is an operational waveform diagram for explanation, and FIG. 12 is a circuit configuration diagram of the receiving device 68. Here, 69... tuner section, 1...
Tuning switch, 2... Encoding means, 75...
...Memo IJ (RAM), 5...Clock oscillator, 83...Square wave generator, 8...
Integral circuit, 25... Increase control terminal, 26...
...down control terminal, 77...sweep voltage generating means, 39...first switching element, 41...
...Second switching element, 40...Third switching element, 42...Fourth switching element, 49,50...Flip-flop, 47,48 ...Logic circuit, 70...
Detection unit, 57... Control circuit, 37...
A rise control switch, 38... a fall control switch.

Claims (1)

[Scope of Claims] 1. A tuner section incorporating a variable capacitance element as a tuning element; A detection section that outputs a DC voltage when the tuner section is tuned; A plurality of components that generate a temporary trigger signal when pressed; a code means following the channel selection switch, which outputs a coded signal corresponding to each of the channel selection switches by operating any one of the channel selection switches; a clock pulse; a clock oscillator that outputs a clock oscillator; a memory that outputs a pre-written storage voltage read out by the coded input signal; A square wave generator that sends out a square wave with a constant period and a duty cycle selected by counting, and an integrating circuit that integrates the output of the previous square wave generator whose duty cycle changes, are grounded. A sweep voltage generator comprising a rise control terminal and a fall control terminal for continuously varying the duty cycle of the square wave from low to high or from high to low only during the period of time. It consists of means and
In a device that performs tuning by applying the output of the sweep voltage generating means to a variable capacitance element of the tuner section, first and second switching elements are connected in series, and a third switching element is also connected in series. and a fourth switching element, and the second switching element
a first holding circuit that holds the switching element; a second holding circuit that holds the third swimming element by the fourth switching element; while pressing the input terminal of the first switching element; a rise control switch which grounds only the middle part, a fall control switch which grounds only the middle part by pressing the input terminal of the third switching element; and a fall control switch which grounds only the middle part by pressing the input terminal of the third switching element; a flip-flop that sends out a reset signal when the tuner section receives the reset signal; and a circuit arrangement that connects the output of the second switching element to the up control terminal and the output of the fourth switching element to the down control terminal. , a logic circuit that is normally kept at H level and transitions to L level only while the rise or fall control switch is pressed; and a logic circuit that changes the output of the second switching element by the output of the flip-flop when the rise control switch is pressed. The output of the fourth switching element is at L level from the moment when the lowering control switch is pressed until a certain frequency is received by the tuner section. An automatic channel selection circuit characterized by comprising a control circuit configured to maintain the same.