JPS5911877B2 - Fast forwarding device for analog electronic clocks - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a time advance device for an analog electronic timepiece, particularly a time advance device 9 that can shorten the adjustment time compared to conventional time advance devices.

As a time correction method for conventional analog electronic watches,
There is a fast forwarding method.

This is a method of correcting the time by applying pulses with a cycle faster than the usual 1 pulse/second to the drive motor of the watch to rapidly advance the hands.

The fast-forward pulse here uses frequency signals such as 8H2° and 16H2 from the middle of the frequency division stage of the conventional clock circuit.

This method has the advantage that the user can easily and accurately adjust the time.

However, this time fast forwarding method has the disadvantage that if the corrected time is significantly different from the displayed time, the time required for fast forwarding is long.

Furthermore, due to problems with followability of the watch drive motor, pulses with very high frequencies could not be used as fast-forward pulses, and there was a limit to the speed of fast-forward.

Incidentally, it is known that the followability of a watch drive motor depends on the magnitude of the load applied to the motor.

Therefore, when the load applied to the motor is small, it is conceivable to shorten the fast-forwarding time by using a pulse with a smaller pulse width and higher frequency than the conventional fast-forwarding pulse as the fast-forwarding pulse.

However, since only a frequency of 2nH2 (n-0, 1, 2-) can be extracted from the frequency division stage, it is inappropriate to use the frequency division stage signal as a fast-forward pulse when the load is small.

The present invention has been made in view of the above-mentioned drawbacks, and its object is to provide a fast-forwarding mechanism in an analog electronic timepiece that can shorten the fast-forwarding time compared to the conventional one.

To achieve the above object, the present invention detects the rotation angle of a fast-forward operation switch and a rotor of a pulse motor in an analog electronic timepiece comprising an oscillation circuit, a frequency dividing circuit, a waveform synthesis circuit, a drive circuit, and a pulse motor. A detection unit, a pulse width control circuit that outputs a signal when the rotation angle of the rotor reaches a predetermined value, and a pulse width control circuit that applies a fast-forward pulse whose pulse width is controlled by the signal of the pulse width control circuit to the drive circuit. The present invention is characterized in that the pulse width of the fast-forward drive pulse is reduced in accordance with the magnitude of the load applied to the pulse motor.

The present invention will be described in detail below based on preferred embodiments.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The oscillator circuit 20 is a circuit that generates a clock driving reference signal, and the frequency divider circuit 22 is a circuit that frequency divides the output signal from the oscillator circuit 20 to IH2.

The waveform synthesis circuit 24 is a circuit that outputs one pulse per second, the pulse width of which is set by the signal from the frequency dividing circuit 22 and the signal from the pulse width control circuit 32.

The drive circuit 26 is a circuit that converts the signal from the waveform synthesis circuit 24 into a drive pulse for the pulse motor 28.

The detection unit 30 is a circuit that detects the rotation angle of the rotor based on the current waveform flowing through the drive coil of the pulse motor 28.

The pulse width control circuit 32 generates a single pulse (
In this embodiment, it is a circuit that outputs a pulse width of 0.degree. 5 μS) to the waveform synthesis circuit 24 and the fast-forward signal generation circuit 34.

The fast-forward signal generation circuit 34 generates a signal from the frequency dividing circuit 22 and the pulse width control circuit 3 when the fast-forward operation circuit 36 is operated.
In this circuit, a correction pulse having a set period is applied to the drive circuit 26 via the waveform synthesis circuit 24 based on the signal from the waveform synthesis circuit 24.

FIG. 2 is a circuit diagram showing an embodiment of the waveform synthesis circuit 24, fast-forward signal generation circuit 34, and fast-forward operation circuit 36 in FIG.

The waveform synthesis circuit 24 is composed of a NAND game) 40, 42° AND gate 44, 46, 48, and an OR gate 50° 52.

Here Nantes Gate 40. -42 constitutes a set-reset flip-flop.

A signal from the output line of the AND gate 44 is applied to one input of the Nant gate 40, and a signal from the output line of the AND gate 44 is applied to one input of the Nant gate 40.
A signal from the output line of the OR gate 50 is applied to one input of the gate.

The IH2 signal 54 from the frequency dividing circuit 22 is applied to one input of the AND gate 44 and the OR gate 50, and the signal from the output line 56 of the pulse width control circuit 32 is applied to the other input.

On the other hand, the AND gate 46 receives 16H from the frequency dividing circuit 22.
2 signal 58.8H2 signal 60.4H2 signal 62.2H2
A signal 64 and a signal on the output line 66 of the Nandt gate 40 are applied.

And and? -) 46 is applied to the drive circuit 26 via the AND gate 48 and the OR gate 52.

The fast-forward signal generation circuit 34 includes a counting circuit 70, a one-shot circuit 72, a flip-flop 74, and an AND gate 76.
．． 78, an OR gate 80, and an inverter 82, and the fast-forward operation circuit 36 is composed of a fast-forward reswitch 84 and a pull-down resistor 86.

Input C of the counting circuit 70 (32-decimal counter in this embodiment)
is configured such that a constant periodic signal 88 (1024H2 in this embodiment) from the frequency dividing circuit 22 is applied via the AND gate 76, and the input R receives the signal from the output line 56 of the pulse width control circuit 32. is applied.

A signal on the output line 90 of the counting circuit 70 and a signal on the output line 56 of the pulse width control circuit 32 are applied to the input C of the flip 70 tube 14 via the OR gate 80.

Further, the signal power of the output line 92 of the one-shot circuit 72 is applied to the input R of the flip-flop 74.

Further, the signal on the output line 94 of the flip-flop 74 is applied to one input of the AND gate γ8.

The signal on the output line 96 of the fast-forward switch 84 is connected to the one-shot circuit 72 and the other input of the AND gate 76,78.
and is applied to the other input of AND gate 48 via inverter 82 .

The signal on the output line 98 of the AND gate 78 is applied to the drive circuit 26 via the OR gate 52.

The operation of this circuit will be explained below.

In this circuit, it is assumed that all flip-flops operate in positive going (positive logic).

When the fast forward switch 84 is open, the signal on the output line 96 is on the low potential side (hereinafter referred to as "low") and the signal on the AND gate 4
8 will be in the open state, and Antoge) 76.78 will be in the closed state.

Here, if the load applied to the pulse motor 28 is large, I
H2 signal 54.2H2 signal 64.4H2 signal 62.8H
The signal on the output line 68 of the AND gate 48 becomes H only when all the 2 signals 60.16H2 signals 58 are on the high potential side (hereinafter referred to as H).

Therefore, a signal in which one pulse with a pulse width of 31.25 m5 is generated per second is obtained on the output line 68 of the AND gate 48.

This single pulse is applied to the drive circuit 26 via the AND gate 48 and the OR gate 52.

This drives the pulse motor 28 to display the time.

When the load applied to the pulse motor 28 is small, the rotor of the step motor 28 reaches a predetermined rotation angle earlier than when the load is heavy.

When the rotor reaches a predetermined rotation angle, a single pulse is generated on the output line 56 of the pulse width control circuit 32.

This single pulse causes the signal on the output line 66 of the Nant gate 40 to fall from H to L.

Therefore, the signal on the output line 68 of the AND gate 46 is 16H.
2 signal 58 goes from H to L before falling from H to L.

As a result, the pulse width of the pulse obtained on the output line 68 of the AND gate 46 is smaller than 31.25 m5.

This pulse is applied to the drive circuit 26 via the AND gate 48 and the OR gate 52 to drive the pulse motor 28.

Below, when the load applied to the step motor 28 is large,
The pulse motor 28 is driven with a drive pulse having a pulse width of 31°25 m5, and when the load is small, the pulse motor 28 is driven with a drive pulse having a smaller pulse width.

When the fast forward switch 84 is closed, the signal on the output line 96 becomes H, the AND gate 48 is closed, and the AND gate 7
6.78 is in an open state.

At the same time, a single pulse is generated on the output line 92 of the one-shot circuit γ2, and the flip-flop 74 is temporarily reset.

As a result, the output line 94 of the flip-flop 74 becomes H.

On the other hand, the counting circuit 70 starts counting the fixed period signal 88 at the same time as the fast forward switch 84 is closed.

Here, when the load applied to the step motor 28 is heavy, the signal on the output line 90 of the counting circuit 70 rises from L to H every 31.25 m5 after the start of counting.

Every time this rising signal is applied to the input C of the flip-flop 740, the signal on the output line 92 alternately becomes L or H and is applied to the drive circuit 26 via the AND gate 78 and the OR gate 52.

Therefore, the drive pulse applied to the pulse motor 28 is a signal with a pulse width of 31.25 mS and a duty ratio of 50%, which is a 16H2 signal.

This drive pulse causes the pulse motor 28 to rotate at high speed, and the time is advanced rapidly.

When the load applied to the pulse motor 28 is small, the rotation angle of the rotor reaches a predetermined magnitude more quickly than when the load is large, and a single pulse is generated on the output line 56 of the pulse width control circuit 32.

Since the counting circuit 70 is temporarily reset by this single pulse, no rising signal is generated on the output line 90.

At the same time, the signal on the output line 94 of the flip-flop 74 changes from H to L.

From this state, the counting circuit 70 again outputs the constant periodic signal 8.
8 starts counting, and after 31.25 m5, the signal on the output line 90 rises from L to H.

This rising signal causes the signal on the output line 94 of the flip-flop 74 to change from L to H, thereby driving the pulse motor 28 again.

Then, if the rotation angle of the rotor reaches a predetermined value before the signal on the output line 90 of the counting circuit 70 rises, the fast-forward pulse generated on the output line 94 is terminated at that point in the same manner as described above.

Therefore, the pulse width of the drive pulse applied to the pulse motor 28 becomes smaller than 31.25 m5, and the period also becomes shorter.

FIG. 3 is a time chart when the fast-forward switch 84 is opened, and FIG. 4 is a time chart when the fast-forward switch 84 is closed.

The numbers shall be in accordance with Figure 2.

According to this embodiment, the fast-forwarding time can be shortened by reducing the pulse width of the drive pulse according to the magnitude of the load applied to the pulse motor 28 and increasing the frequency of the fast-forwarding pulse.

Furthermore, when the load applied to the pulse motor 28 increases, the frequency of the fast-forward pulse is fixed at 16H2.

In this embodiment, the maximum pulse width of the fast-forward pulse is 31.25 m5, but this value is determined by the frequency dividing circuit 22.
It can be set freely by changing the constant period signal 88 and the counting circuit 70.

As described above, according to the present invention, by reducing the pulse width of the fast-forward pulse according to the magnitude of the load applied to the step motor, the fast-forward time can be shortened compared to the conventional analog electronic clock. equipment can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram of the waveform synthesis circuit and fast-forward signal generation circuit in FIG. 1, and FIGS. 3 and 4 are time charts thereof. 24... Waveform synthesis circuit, 30... Detection section, 32...
・Pulse width control circuit, 34... fast forward signal generation circuit,
36...Fast forward operation circuit, 70...Counting circuit, 72
゛... One-shot circuit, 74... Flip-flop, 76.78... AND gate, 80... OR gate, 82... Inverter.

Claims (1)

[Scope of Claims] 1. An analog electronic timepiece comprising an oscillation circuit, a frequency dividing circuit, a waveform synthesis circuit, a drive circuit, and a pulse motor, including a fast-forward operation switch, a detection unit that detects the rotation angle of the rotor of the pulse motor, a pulse width control circuit that outputs a signal when the rotation angle of the rotor reaches a predetermined value; and a fast-forward signal generation circuit that applies a fast-forward pulse whose pulse width is controlled to the drive circuit according to the signal from the pulse width control circuit. has
A time advance device for an analog electronic watch, characterized in that the pulse width of a drive pulse for fast advance is reduced in accordance with the magnitude of the load applied to a pulse motor. 2. Claim 1, characterized in that the waveform synthesis circuit is configured to reduce the pulse width of the normal clock drive pulse applied to the pulse motor according to the size of the load. A fast-forwarding device for analog electronic watches.