JPS5911938B2 - signal matching device - Google Patents
signal matching deviceInfo
- Publication number
- JPS5911938B2 JPS5911938B2 JP49103357A JP10335774A JPS5911938B2 JP S5911938 B2 JPS5911938 B2 JP S5911938B2 JP 49103357 A JP49103357 A JP 49103357A JP 10335774 A JP10335774 A JP 10335774A JP S5911938 B2 JPS5911938 B2 JP S5911938B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- gate
- selection mechanism
- terminals
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
Description
【発明の詳細な説明】
本発明は受動回路網を設けた記憶素子を接続することに
より、記憶素子より供給される特定の信号と、あらかじ
め選択機構に設定されているコードとを比較し、両者が
一致したときにのみ出力する信号照合装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention compares a specific signal supplied from the memory element with a code set in advance in the selection mechanism by connecting memory elements provided with a passive circuit network, and compares both signals. The present invention relates to a signal matching device that outputs an output only when there is a match.
このような信号照合装置は、たとえば外部よりの入力信
号とあらかじめ内部に設定したコードとを照合後、出力
した開錠信号により、ソレノイド駆動で開錠作動を行う
開錠装置のように、簡単な構造で安価に作成でき、しか
も作動が確実な必要がある装置に使用できる。Such a signal matching device is a simple lock-opening device that uses a solenoid drive to open the lock using the output signal after comparing an input signal from the outside with a code set internally. It has a structure that can be manufactured at low cost and can be used in devices that require reliable operation.
従来、信号照合装置としては、磁気カード、磁気ヘッド
、増幅回路、波形整形回路、レジスタ回路、信号照合回
路とから成り立つたものがあるが、回路も複雑で高価で
ある。Conventionally, signal verification devices include a magnetic card, a magnetic head, an amplifier circuit, a waveform shaping circuit, a register circuit, and a signal verification circuit, but the circuits are complicated and expensive.
本発明は簡単に構成されて、動作が確実でありク価格も
安い特徴がある。The present invention is characterized by a simple structure, reliable operation, and low cost.
以下、本発明を図面に示す実施例により説明する。絶縁
体１に受動回路網２を設けて記憶素子３となしてあり、
受動回路網２は出力端子Ｔ１、Ｔ３−−−を電源端子Ｔ
Ｂに、出力端子Ｔ２、Ｔ４−−−ＴＮを電源端子ＴＡに
直列に結線して形成してある。The present invention will be explained below with reference to embodiments shown in the drawings. A passive circuit network 2 is provided on an insulator 1 to form a memory element 3,
The passive circuit network 2 connects the output terminals T1, T3--- to the power supply terminal T.
At B, output terminals T2, T4 ---TN are connected in series to the power supply terminal TA.
照合部４には出力端子Ｔ１〜ＴＮと対応する入力端子１
１〜１Ｎと、電源端子ＴＡ、ＴＢに対応する電源端子Ｉ
Ａ、ＩＢを設けてある。The collation unit 4 has an input terminal 1 corresponding to the output terminals T1 to TN.
1 to 1N, and power terminal I corresponding to power terminals TA and TB.
A and IB are provided.
電源端子ＩＡはプラス電源に接続し、電源端子ＩＢは接
地してある。入力端子１１〜１Ｎはそれぞれインバータ
Ｖ１〜ＶＮの入力側に接続し、インバータＶ１〜ＶＮの
出力はそれぞれ選択機構５のスイッチ５１〜５Ｎになさ
れる。スイッチ５１〜５Ｎは５それぞれ端子Ａ１、０１
〜端子ＡＮ、ＯＮに切換え可能となつており、端子Ａ１
〜ＡＮはアンドゲート６の入力側に、端子０１〜０Ｎは
オアゲートＴの入力側に接続してある。アンドゲート６
はナンドゲート８に、オアゲートＴはナンドゲート９を
介してナンドゲート８に接続してある。本発明の装置の
作動について説明すると、記憶素子３の出力端子Ｔ１〜
ＴＮ、および電源端子ＴＡ、ＴＢをそれぞれ照合部４の
入力端子１１〜１Ｎ、および電源端子ＩＡ、ＩＢに接続
すると、５電源端子ＩＡ、ＩＢより電源端子ＴＡ、ＴＢ
にレベル゛１″ｂ″の電源が供給され、出力端子Ｔ１、
Ｔ３−−−にレベル゛ｏ″、出力端子Ｔ２、Ｔ４−ー一
ＴＮにレベルゞ１２の信号が出力され（レベルゞ０Ｉ，
Ｓ１″は受動回路網２の結線パターンにより適宜選択で
きる。）、その信号は入力端子１１〜ＩＮに伝達される
。選択機構５ではあらかじめスイツチＳｌ，Ｓ３−ー一
をそれぞれ端子Ａｌ，Ａ３に、スイツチＳ２，Ｓ４−ー
一ＳＮをそれぞれ端子０２，０４−ー一ＯＮにスイツチ
ングしてコードを設定してある。入力端子１１〜ＩＮか
らの各信号はインバータＶ１〜ＶＮおよび選択機構５を
経ておのおのアンドゲート６およびオアゲート７に伝達
されるが、入力端子２，４−ー一Ｎに入力する信号がす
べてレベルゞ１″のときにのみオアゲート７はレベルＳ
Ｏ７を出力し、入力端子１１，１３−ー一に入力する信
号がすべてレベルＳＯ〃のときにのみアンドゲート６は
レベルゞ１２を出力する。Power supply terminal IA is connected to a positive power supply, and power supply terminal IB is grounded. Input terminals 11-1N are connected to the input sides of inverters V1-VN, respectively, and outputs of inverters V1-VN are sent to switches 51-5N of selection mechanism 5, respectively. Switches 51 to 5N are terminals A1 and 01, respectively.
~It is possible to switch between terminals AN and ON, and terminal A1
~AN is connected to the input side of the AND gate 6, and terminals 01 to 0N are connected to the input side of the OR gate T. and gate 6
is connected to the NAND gate 8, and the OR gate T is connected to the NAND gate 8 via the NAND gate 9. To explain the operation of the device of the present invention, the output terminals T1 to T1 of the memory element 3
When TN and power terminals TA and TB are connected to the input terminals 11 to 1N of the matching section 4 and the power terminals IA and IB, respectively, the power terminals TA and TB are connected from the 5 power terminals IA and IB.
A level "1"b" power is supplied to the output terminals T1,
A signal of level ゛o'' is output to T3----, and a signal of level 12 is output to output terminals T2 and T4--TN (level 0I,
S1'' can be selected as appropriate depending on the connection pattern of the passive circuit network 2), and the signal is transmitted to the input terminals 11 to IN.The selection mechanism 5 connects switches S1 and S3--1 to terminals Al and A3, respectively, in advance in the selection mechanism 5. The codes are set by switching switches S2, S4--SN to terminals 02, 04--1, respectively, to ON.Each signal from input terminals 11-IN passes through inverters V1-VN and selection mechanism 5, respectively. The signal is transmitted to the AND gate 6 and the OR gate 7, but the OR gate 7 outputs the level S only when all the signals input to the input terminals 2, 4--1N are at the level 1''.
AND gate 6 outputs level 12 only when all signals input to input terminals 11, 13--1 are at level SO.
このように選択機構５によるコード設定内容と記憶素子
３の出力端子Ｔ１〜ＴＮから供給される信号パターンと
が全く一致したときにのみアンドゲート６にレベル′１
″の出力がオアゲート７にレベルゞ０Ｉの出力がでてく
ることになる。オアゲート７から出力されたレベルゞ０
Ｉの信号はナンドゲート９により反転され、レベルゞ１
″の信号となつてナンドゲート８に入力する。アンドゲ
ート６から出力されたレベルゞ１″の信号はナンドゲー
ト８に入力され、ナンドゲート８はそれぞれ入力した信
号がレベルゞ１″のときにのみ作動してレベルゞ０″の
信号を出力する。なお、インバータＶ１〜ＶＮは入力端
子１１〜ＩＮ側から、選択機構５で設定したコードを探
索できないようにするため設けてある。In this way, only when the code setting contents by the selection mechanism 5 and the signal pattern supplied from the output terminals T1 to TN of the storage element 3 completely match, the AND gate 6 is set to the level '1.
'' output will be output at level 0I to OR gate 7. Level 0I output from OR gate 7
The signal of I is inverted by the NAND gate 9 and becomes level 1.
'' signal and input to the NAND gate 8. The level 1'' signal output from the AND gate 6 is input to the NAND gate 8, and each NAND gate 8 operates only when the input signal is at level 1''. outputs a level 0'' signal. Note that the inverters V1 to VN are provided to prevent the code set by the selection mechanism 5 from being searched from the input terminals 11 to IN side.
インバータＶ１〜ＶＮが設けてない場合には選択機構５
の接続関係が知られてしまうが、前記のようにインバー
タ１〜ＶＮを入れておけばこの回路の入力端子１１〜Ｉ
Ｎは同じ電位となるから選択機構５の接続関係を他人に
みきわめられないようにすることができる。If inverters V1 to VN are not provided, selection mechanism 5
However, if the inverters 1 to VN are inserted as described above, the input terminals 11 to I of this circuit will be known.
Since N has the same potential, the connection relationship of the selection mechanism 5 can be prevented from being discerned by others.
本発明は以上のように、受動回路網を設けた簡単な構造
の記憶素子により、照合部に特定の信号を送出し、選択
機構のコードと対応させ、信号とコードとが一致したと
きにのみゲート回路のゲートを開くようにしてあるから
、記憶素子の受動回路網の結線状態を種々に変えれば、
いくとおりもの組合せができ、それに対応してコードと
なる選択機構を切換えればよいので、簡単な装置で信号
照合ができる。As described above, the present invention uses a storage element with a simple structure provided with a passive circuit network to send a specific signal to the collation unit to make it correspond to the code of the selection mechanism, and only when the signal and the code match. Since the gate of the gate circuit is opened, if the connection state of the passive circuit network of the memory element is changed in various ways,
Since a number of combinations can be made and the selection mechanism that becomes the code can be switched accordingly, signal verification can be performed with a simple device.
また磁気カードを用いた信号照合装置のように書込み、
読出し時に媒体や・＼ツドの駆動装置その他の機械的運
動部分や、複雑な電子回路を用いないで、安定で確実、
安価に信号照合ができる。It also writes like a signal verification device using a magnetic card,
It is stable, reliable, and does not require the use of media, drive devices, other mechanically moving parts, or complex electronic circuits during readout.
Signal verification is possible at low cost.
第１図は本発明装置に使用する記憶素子の回路図、第２
図は同装置の回路図である。
２・・・・・・受動回路網、３・・・・・・記憶素子、
５・・・・・・選択機購、６・・・・・・アンドゲート
、７・・・・・・オアゲート、８，９・・・・・・ナン
ドゲート。Figure 1 is a circuit diagram of a memory element used in the device of the present invention;
The figure is a circuit diagram of the device. 2...passive circuit network, 3...memory element,
5...Selection machine purchase, 6...And gate, 7...Or gate, 8,9...Nand gate.
Claims (1)
る受動回路網を設けた記憶素子に、前記記憶素子の電源
端子に接続する電源端子と、前記記憶素子の出力端子に
接続する入力端子と、前記入力端子にコード探索禁止に
コード探索禁止インバータを介して接続し、前記記憶素
子からの特定入力信号と対応するコードを設定可能な選
択機構と、前記選択機構に接続されたゲート回路とを備
えた照合部を組合せてなり、前記記憶素子からの入力信
号と前記選択機構のコードとが一致したときにのみ前記
照合部のゲートを開くようにした信号照合装置。1. A memory element provided with a passive circuit network consisting of a power supply terminal and an output terminal connected to the power supply terminal, a power supply terminal connected to the power supply terminal of the memory element, and an input terminal connected to the output terminal of the memory element, A selection mechanism connected to the input terminal via a code search inhibition inverter to inhibit code search and capable of setting a code corresponding to a specific input signal from the storage element, and a gate circuit connected to the selection mechanism. 2. A signal verification device comprising a combination of a verification section and a gate of the verification section opened only when an input signal from the storage element matches a code of the selection mechanism.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49103357A JPS5911938B2 (en) | 1974-09-07 | 1974-09-07 | signal matching device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49103357A JPS5911938B2 (en) | 1974-09-07 | 1974-09-07 | signal matching device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5130457A JPS5130457A (en) | 1976-03-15 |
| JPS5911938B2 true JPS5911938B2 (en) | 1984-03-19 |
Family
ID=14351869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49103357A Expired JPS5911938B2 (en) | 1974-09-07 | 1974-09-07 | signal matching device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5911938B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5311183B2 (en) * | 1972-07-27 | 1978-04-19 |
-
1974
- 1974-09-07 JP JP49103357A patent/JPS5911938B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5130457A (en) | 1976-03-15 |
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