JPS5912028B2 - Manufacturing method for semiconductor devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a MOS type transistor having a self-adjusting structure or a MOS type IC.

Generally speaking, an insulated gate field effect transistor or a MOS type IC incorporating the same is n(p), as shown in FIG.
) type Si substrate 11 has a source 12 and drain 13 regions formed by diffusion of p+10 (n+) type impurities on the main surface, and an insulating film (dielectric) 14 is formed on the Si surface sandwiched between these two regions. Conventionally, a conductor is formed on the insulating film to form a gate electrode G, and a source electrode S and a drain electrode D are provided in parallel with each other as shown in FIG. 15 to be ohmically connected to the two regions. In such a semiconductor device, the conductivity of the channel portion 2015 that is induced on the semiconductor surface between the source and drain by the voltage between the gate and the substrate or that already exists is changed, but the insulating film of the gate portion It is well known that by forming 14 thin, the threshold voltage can be lowered and characteristics such as mutual conductance can be improved. Therefore, in the conventional insulated gate field effect transistor 25, the insulating film 16 on other parts of the substrate, that is, the insulating film 16 for protecting the Pn junction end, is formed with a sufficient thickness, whereas the gate part Usually, a thin insulating film is formed in a separate process.

However, in general, the width and length of the gate 30 electrode G and the gate insulating film 14 must be set to appropriate values due to manufacturing precision, and since the gate insulating film is thin, there is a gap between the gate and the substrate. In this case, the capacitance coupling between the gate and the drain had to be increased unnecessarily, which impeded the operating characteristics35. Naturally, one way to reduce the effects of such capacitive coupling is to minimize the distance between the overlapping part of the conductor (gate) and drain region on the insulating film. There was a technical problem in that it was difficult to precisely align the mask patterns used in photoetching (in which a photo-etching method was used).
In the MOS structure manufactured by the conventional method described above, there is also a problem with the junction capacitance between the drain and the substrate, and an increase in this is not good in terms of frequency characteristics.

In addition, in the case of a MOS type IC in which a large number of elements of the above MOS structure are arranged on one substrate, a sufficient distance between the elements should be maintained in consideration of the lateral spread of the depletion layer from the drain during operation. For this reason, there were many problems that needed to be solved in practical soil, such as the inability to sufficiently increase the density. The present invention has been made to solve the above-mentioned problems.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can form an oxide layer buried in a semiconductor substrate and a recessed portion with a predetermined size and a predetermined positional relationship. Hereinafter, an example in which the present invention is applied to a MOS type 1C will be specifically described. First, the process order will be explained with reference to FIG. (a) High resistivity n-type (or P-type) S
The entire surface of i (silicon) substrate (wafer) 1 is 11CP+ type (
A Si layer 2 having a specific resistance lower than this is formed.

This P(n) type Si layer 2 may be formed by any of the diffusion method, impurity doping method, and epitaxial growth method. The thickness of the Si layer is approximately 1 to 2 μm.
5(b) P(n) type S
A mask 3 made of an oxidation-resistant material is formed on the surface of the i-layer 2. This oxide resistant material is a material that suppresses the oxidation of Si immediately below it when oxidation treatment is performed, such as an insulating material such as Si3N4 (silicon nitride), Al2O3 (alumina), or Al
Metals such as these can be considered. When using Si3N4, the thickness should be about 2000 to 3000A, and especially SiO2 or SiO2 should be used as a protective film for completed semiconductor devices.
If a double thick film of 2 and Si3N4 is required, it is preferable to use a double layer of SiO2 as the base 4 and cover it with Si3N4.

When Al is used, it is used as Al2O3 by oxidation treatment after mask formation. Such an oxidation-resistant material is first formed as a film over the entire surface of the Si substrate, then subjected to photoresist treatment, and unnecessary portions are removed using a predetermined mask pattern. The portion left as a mask is the portion where the source region and drain region of the MOS device are to be formed, and is also left as the portion where a cross-under resistance portion at the element boundary portion is to be provided as required. (c) Next, the above Si
The substrate 1 is heated to a temperature of 1000 to 1000 in an oxidizing atmosphere, e.g.
By performing a heat treatment at 1200° C. for several hours, the surface of the substrate 1 is oxidized in a portion to which the oxide-resistant mask is not attached, and an oxide layer 4 is selectively formed in that portion.

The depth at which this SiO2 silicon oxide layer 4 is formed is:
The depth is required to be at least larger than the depth of the p+ type Si layer 2, for example, 1.5 to 2.5μ. This SiO
By forming two layers, the P+ type Si layer 2 becomes the source region 2a.
(d) The SiO2 layer in the part sandwiched between the source region 2a and the drain region 2b, that is, the part corresponding to the gate, is separated into several regions including the drain region 2b and the drain region 2b. The concave portion 5 is formed by etching until it reaches 1.

At this time, the oxide layer 4 other than the portion where the recessed portion 5 is formed
A photoresist 9 is used on the surface as shown in the figure. For this etching, use an etching solution that easily attacks SiO2 but does not attack Si, such as a mixture of nitric acid: acetic acid: glacial acetic acid = 1:4:9. Etching is performed until the top surface of the Si substrate is exposed. (e) by heating in a humid oxygen atmosphere;
New S is added to the inner surface of the recess 5 where the Si surface was exposed in the above process.
The iO2 film 6 is thermally generated.

This SiO2 film 6 is a portion to become a gate insulating portion, and is formed into a thin insulating film having a thickness of about 1000 to 2000 Å.

(f) By photo-etching, a part of the Si3N4 film 3 is selectively removed to expose a part of the source region 2a and drain region 2b, and then aluminum is deposited on the entire surface in a high vacuum. forming a conductor layer;
Unnecessary portions of aluminum are removed by photo-etching again, and a gate electrode G is placed on the source electrode S drain electrode D and the thin SiO2 film, and wiring is formed between them to complete MOS type 1C. do.

A part of the wiring can be connected to a part 7 of the P+ type Si layer existing at the boundary of the MOS element and used as a cross-under resistor.

As described above with reference to Examples, the manufacturing method of the present invention is more advantageous than the conventional method in the following respects.

(1) To form the oxide layer buried in the semiconductor substrate and the recess, patterning and oxide layer formation are performed simultaneously using a Si2N4 mask, and then a part of the oxide is removed to form the recess. Since the oxide layer and the recessed portion can be formed in a predetermined size and in a predetermined positional relationship, the oxide layer and the recessed portion can be formed with a predetermined size and a predetermined positional relationship.

(2) In particular, in the manufacture of MOS type 1C, the SiO2 layer 4 formed using an oxide-resistant mask allows reliable electrical isolation between individual MOS elements, reducing the junction capacitance between the drain and the substrate. It can contribute to stability.

(3) Similarly, in the case of MOS type 1C manufacturing, individual MOS elements are separated by the SiO2 layer 4 formed using an oxide-resistant mask, so there is no need to consider increasing the element spacing, and the integration is increased. can be increased.

(4) By performing etching with the oxide resistant film present on the P+ (n+) type semiconductor layer to open the recess 5 and forming the thin insulating film 6 along the inner surface of the recess, The overlapping width of the gate and drain can be reduced.

That is, by cutting the side surfaces of the source and drain regions vertically using the recessed portions, providing the thin insulating film 6 on the side surfaces, and providing the gate conductor on top of the thin insulating film 6, the gate and drain regions are separated. The overlap corresponds to the vertical depth of the drain region. Since this depth is formed to be extremely small dimensionally, the capacitive coupling between the gate and the drain is extremely small, and can be reduced to about one-tenth of the conventional depth. (5) From (4), there is no need to particularly precisely define the gate position relative to the drain when forming the gate conductive portion, and as an insulated gate semiconductor device with a self-adjusting structure,
High integration and high speed became possible.

(6) Although the PN junctions are separated by grooves, the surface of the semiconductor substrate is almost flat due to the oxide film 4, and on the surface on which electrodes are extended or on which wiring is formed in an IC, No step portions are formed in the wiring, and there is no adverse effect due to non-uniform deposition, for example, at step portions of metal vapor deposition. (7) The recessed portion 5 between the source and drain regions is formed by etching the oxide layer 4. As an etchant for etching SiO2, it is possible to select an etchant that has an etch rate several hundred to several thousand times higher than that of Si, thus making the dimensional accuracy of the recessed portion 5 extremely high. be able to.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of an example of an insulated gate transistor manufactured by a conventional method, and FIG. 2 is a vertical cross-sectional view of a semiconductor device at each step showing the manufacturing process according to the method of the present invention. DESCRIPTION OF SYMBOLS 1...n(p) type Si substrate, 2...P+(n+) type Si layer, 3...oxidation-resistant film (Si3N4 film) mask, 4
... Oxide (SiO2) layer, 5... Concave portion, 6...
- Thin insulating film (SiO2 film), 9... photoresist.

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor device, in which an oxide layer buried in the semiconductor substrate and a recess are formed on one main surface of the semiconductor substrate, the oxide layer and the recess on one main surface of the semiconductor substrate are formed. The oxidation layer formation portion and the recess formation portion are patterned by forming an oxidation-resistant mask on the portion other than the portion where the oxide layer is to be formed, and then the portion where the oxide layer is to be formed and the recess formation are patterned using the mask. The oxide layer to be buried in the semiconductor substrate and the oxide layer formed in the portion to form the recess are then buried in the semiconductor substrate. An etching-resistant mask is formed on the oxide layer to be formed, and the recess is formed by utilizing the difference in etching rate between the oxide layer formed in the area where the recess is to be formed and the semiconductor substrate. manufacturing a semiconductor device, characterized in that the oxide layer and the recessed portion are formed in a predetermined size and in a predetermined positional relationship by selectively removing the oxide layer formed in the desired portion; Law.