JPS5912066B2 - television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is suitable for use, for example, in measuring the state of track switching in a video tape recorder, or in measuring the state of superimposition of three colors of video signals from a color television camera. Regarding television receivers.

When performing measurements such as those described above, it is necessary to monitor the signal during the vertical blanking period of the television signal.

To do this, the vertical blanking period is displayed in the center of the screen on a television receiver for monitoring. Various methods have been proposed to perform this monitoring. One method for this is to first delay the video signal by 5 times using a delay circuit. However, when this method is used, the S/M ratio of the video signal deteriorates significantly in the delay circuit. On the other hand, there is a method 0 in which the vertical deflection frequency is the same and the vertical blanking period between fields is monitored. The drawback is that you can only see the vertical blanking period on one side or the other.

Also, in order to ensure reliable monitoring, it may be necessary to enlarge the projected screen by 15 degrees.

One method for this is to amplify the vertical deflection current so that only a portion of the television signal is used to scan the entire screen. However, with this method, the remaining electron beams that are not scanned onto the screen hit the funnel of the cathode ray tube.
! 0 Unnecessary images appear on the screen due to the reflection. Furthermore, there is a method of applying a limiter to the amplified vertical deflection current in order to prevent the electron beam from hitting the funnel section, but in this case, the electron beam is continuously passed on the same scanning line at the top and bottom edges of the screen. 95-mm is scanned, which is undesirable because it causes burn-in of the phosphor. In view of these points, the present invention eliminates the above-mentioned conventional drawbacks, allows any part of the video signal to be displayed on the screen, and
This was further expanded to include 30 monitors.

That is, the present invention provides n times the reference horizontal or vertical deflection frequency (n
1), a deflection signal forming circuit for forming a horizontal or vertical deflection signal with a frequency of or a blanking circuit for blanking the video signal in a horizontal or vertical deflection period other than every n-th horizontal or vertical deflection period of the vertical deflection signal, and By supplying every nth video signal to the cathode ray tube, an image that is n times larger than the normal screen is displayed.

An embodiment of the present invention will be described below with reference to the drawings.
A case will be described in which, in a C format television signal, the signal during the vertical blanking period of the signal is displayed in the center of the screen and further enlarged for monitoring.

Figure 1 is an overall system diagram.

In the circuit shown in Figure 1, by changing the switch, you can obtain a normal screen, a screen with the vertical blanking period projected in the center of the screen, and a screen with the vertical blanking period expanded in the center of the screen. This shows the case when In the figure, reference numeral 1 denotes an input terminal to which a television signal from a video tape recorder, television camera, etc. is supplied, and this human input terminal is connected to a synchronization separation circuit 2.

The output terminal of this synchronous separation circuit 2 is connected to the . - Connect to a monostable multivibrator (hereinafter abbreviated as mono-multi) 3, which has a pulse width of one horizontal period H, and the output terminal of this mono-multi vibrator 3 is connected to an inverter 4 with a pulse width of one horizontal period. Connect to H's Mono Multi 5.

The mono-multi 8 VC. Connecting. The output terminal of this monomulti 8 is connected to seven flip-flop circuits (hereinafter abbreviated as FF) in series via an inverter 9. Connect to the configured 7-digit binary counter 10. 11 is a pulse signal generation circuit, and synchronous separation circuit 2f1C. This circuit generates a pulse signal that starts at one horizontal period H at the tip of the vertical synchronizing signal in the synchronizing signal and falls after a slightly shorter period of three horizontal periods H.

The output terminal of this pulse signal generation circuit 11 is connected to a binary
Each FF set terminal FlC. of the counter 10. Connecting. In addition, the output terminal of the binary counter 10 is connected to two F
The reset terminal of this binary counter 12 is connected to the output terminal Vr.F of the pulse signal generating circuit 11. Connecting. Further, the output terminal of the binary counter 12 is connected to FF14 through an inverter 13, the reset terminal of this FF14 is connected to the output terminal of the pulse signal generation circuit 11, and the output terminal of FF14 is connected through a series circuit of an inverter 15 and a switch 16. The buffer is connected to the amplifier 17. Further, the output terminal of FF14 is directly connected to the buffer amplifier 17 through the switch 18. Furthermore, the output terminal of the binary counter 12 is connected to FF19, and this F
The reset terminal of Fl9 is connected to the output terminal of the pulse signal generation circuit 11, and the output terminal of Fl9 is connected to the first input terminal of the NAND circuit 21 through the inverter 20. Further, the output terminal of the burner counter 10 is connected to the second human power terminal of the NAND circuit 21, and the output terminal of the NAND circuit 21 is connected to the buffer amplifier 17VC. Connecting. The output terminal of this buffer amplifier 17 is connected to a monomulti 24VC. Connect the output terminal of this monomulti 24 to the synchronous pulse amplifier 26K through the inverter 25.
This synchronized pulse amplifier 26 leads out an output terminal 27 for connection to the oscillator of the vertical deflection circuit.

Furthermore, the output terminal of the NAND circuit 21 is connected to the FF 28, the set terminal of this FF 28 is connected to the output terminal of the pulse signal generation circuit 11, and the output terminal of this FF 28 is connected to the FF 29.
The reset terminal of this FF 29 is connected to the output terminal of the pulse signal generation circuit 11, and the output terminal of this FF 29 is connected to the first input terminal of the NAND circuit 30.

Further, the output terminal of the FF 28 is connected to the second human input terminal of the NAND circuit 30. Further, the output terminal of the inverter 25 is connected to a third human power terminal of a NAND circuit 30, and the output terminal of this NAND circuit 30 is connected to a blanking circuit 32 through a switch 31r that interlocks with the above-mentioned switch 23. An output terminal 33 is led out from the circuit 32 to connect to a brightness circuit of a video signal system. In the circuit shown in FIG. 1 described above, a television signal is supplied to the human power terminal 1 by Vc. The output terminal of the synchronization separation circuit 2 has a second
A synchronizing pulse signal Pa as shown by AVC in the figure is obtained.

Figure 2 shows the vertical blanking period of a television signal, where T is the vertical synchronization pulse period;
T2 and T3 indicate the equalization pulse period, and T4 indicates the horizontal synchronization pulse period, respectively. By supplying this synchronous pulse signal Pa to the monomulti 3VC, the monomulti 3VC
The output terminal of BVC. A pulse signal Pb of the same frequency is obtained in synchronization with the horizontal synchronizing signal over the entire period of the television signal as shown.

The inverter 4 inverts the phase of this pulse signal Pb and supplies it to the monomulti 5. The output terminal of the monomulti 5 receives each horizontal synchronizing pulse in the synchronizing pulse signal Pa as shown in C in FIG. Pulse signal P falling in the middle
c is obtained.

In the signal obtained by inverting the phase of this pulse signal Pc and the pulse signal Pb described above, the falling edge of each signal is extracted and the monomulti 8Vc. supply In this way, a pulse signal Pd having a frequency twice the frequency of the horizontal synchronizing pulse (horizontal deflection frequency) as shown in D in FIG. 2 is obtained at the output terminal of the monomulti 8. This pulse signal Pd is transferred to the inverter 9
The phase is inverted by the binary counter 10VC. supply Further, a pulse signal Pe as shown in FIG. In this way, this binary counter 10 starts counting after the end of the vertical synchronization pulse period T1 of the synchronization pulse Pa, that is, from the trailing edge of the vertical synchronization signal, and starts counting at the -horizontal period (-
In this case, one field of the television signal is 262.
5 horizontal periods (262.5H).

Therefore, in one field period, the binary counter 1
At the output terminal 0, there are 4 periods of pulse signals each having 64 horizontal periods (64H), and then 3.5 horizontal periods (3.5H).
The pulse signal Pf as shown in A in FIG. 3 is composed of one pulse having the same pulse width T6 as the pulse width for 3 horizontal periods (3H) from the pulse signal generation circuit 11 generated after the period T5 of 5H) minutes. is obtained. This pulse signal Pf is supplied to the binary counter 12, and the pulse signal generation circuit 11
7) By supplying the pulse signals Pe from the
BVC in the figure. A pulse signal Pg as shown is obtained.

This pulse signal Pg is phase inverted by an inverter 13 and F
By supplying the pulse signal Pe from the pulse signal generation circuit 11 to the reset terminal,
The output terminal of 4 receives a pulse signal Ph as shown in C in Fig. 3.
is obtained. Further, the pulse signal Pg is directly supplied to FF19, and the pulse signal Pe from the pulse signal generation circuit 11 is supplied to the reset terminal, and the output terminal of FF19 is supplied with a pulse signal Pi as shown in D in FIG. is obtained.
Furthermore, this pulse signal Pi is connected to an inverter 20VC. By supplying the phase-inverted signal and the above-mentioned pulse signal Pf to the NAND circuit 21, the output terminal of the NAND circuit 21 receives the EflC. A pulse signal Pj as shown is obtained.

These pulse signals Ph and Pj are switched to switches 16 and 18.
and 23 VC are selectively supplied to the subsequent circuit.

The following explanation will be given separately for each case. First, when the switch 16 is turned on, the pulse signal Ph is phase-inverted by the inverter 15, further phase-inverted by the buffer-amplifier 17, and then supplied to the monomulti 24. That is, the AVC in FIG. As shown in FIG. 3C, a pulse signal Phl having the same phase as the pulse signal Ph shown in FIG. 3C is supplied to the monomulti 24. From this, the output terminal FlC. of the monomulti 24.
A pulse signal Pkl as shown by BVC in FIG. 4 is obtained. The phase of this pulse signal Pk is inverted by an inverter 25, amplified by a synchronous pulse amplifier 26, and supplied through an output terminal 27 to an oscillator of a vertical deflection circuit. A vertical deflection current 1, as shown in FIG. 4C, is thus obtained in the oscillator. In this case, the position of the synchronization signal (pulse signal Pk,) supplied to the oscillator is delayed by 131 horizontal periods (131H) from the position of the vertical synchronization signal of the television signal.

Therefore, deflection is performed using the vertical deflection current 11 obtained from this oscillator VC. The 135th scanning line counting from the vertical synchronization signal of the television signal is at the top and the 131st scanning line is at the bottom. The ranking period will be displayed.
Next, when the switch 18 is turned on, the pulse signal Ph
is phase-inverted by the buffer amplifier 17, and the monomulti 2
4. That is, the AVC. By supplying a pulse signal Ph2 obtained by inverting the phase of the pulse signal Ph as shown to the monomulti 24, a pulse signal Pk2 as shown in B in FIG. 5 is obtained at the output terminal of the monomulti 24. This pulse signal Pk2 is supplied to the oscillator of the vertical deflection circuit in the same manner as described above. Thus, a vertical deflection current 12 as shown in FIG. 5C is obtained in the oscillator. In this case, the synchronization signal (pulse signal Pk
The position 2) is equal to the position of the vertical synchronization signal of the television signal. Therefore, the vertical deflection current 12 obtained from this oscillator is equivalent to the vertical deflection current obtained by synchronously separating the television signal as it is. screen will be displayed. Furthermore, when the switch 23 is turned on, the pulse signal P
j is phase-inverted by the inverter 22, further phase-inverted by the buffer amplifier 17, and supplied to the monomulti 24.
That is, as shown in FIG. 6A, a pulse signal Pj3 having the same phase as the pulse signal Pj is transmitted to the monomulti 24VC. The output terminal of the monomulti 24 is connected to the BVC.
A pulse signal Pk3 as shown is obtained. This pulse signal Pk3fr is supplied to the oscillator of the vertical deflection circuit in the same manner as described above. Thus, a vertical deflection current 13 as shown in FIG. 6C is obtained in the oscillator. Further, when the switch 31 is turned on, a signal is supplied to the blanking circuit 32.

That is, the pulse signal Pj is supplied to the FF 28, and the pulse signal Pe from the pulse signal generation circuit 11 is supplied to the reset terminal FlC. Therefore, a pulse signal Pm as shown in D in FIG. 6 is obtained at the output terminal of the FF 28. By supplying this pulse signal Pm to the FF29VC and supplying it to the pulse signal Pefr reset terminal from the pulse signal generation circuit 11, a pulse signal Pn as shown in E in FIG. 6 is obtained at the output terminal of the FF29. . VC. Therefore, a pulse signal Pp as shown in F in FIG. 6 is obtained at the output terminal of the NAND circuit 30.

This pulse signal Pp is supplied to the blanking circuit 32.

In this case, the synchronization signal (pulse signal P
The position of k3) is a position delayed by 35 horizontal periods (35H) from the position of the vertical synchronization signal of the television signal, and 64 times thereafter.
There are a total of four locations for each horizontal period (64H).

In response to this synchronization signal, the oscillator generates a sawtooth wave with the same amplitude as in the normal case. Therefore, by performing deflection using the vertical deflection current 13 obtained from this oscillator, the 38th signal on the screen, counting from the vertical synchronization signal of the television signal, is displayed on the screen.
The 102nd, 166th, and 230th scanning lines are at the top, and the 99th, 163rd, 227th, and 35th
The video signal is scanned with the th scanning line at the bottom,
Furthermore, blanking is performed by the pulse signal PpV
C. Thus, an image is displayed on the screen, with the 230th scanning line counting from the vertical synchronization signal of the television signal at the top and the 35th scanning line at the bottom. As described above, the television receiver VC of the present invention. If it is possible, by performing deflection using a horizontal or vertical deflection signal with the horizontal or vertical deflection frequency multiplied by an arbitrary number of times (n>l), it is possible to enlarge the portion of the video signal by an arbitrary number of times and project it. In addition, by blanking unnecessary parts, the electron beam hits the funnel of the cathode ray tube and a reflected image is generated, and the phosphor is removed by continuously scanning the same scanning line. There is no burn-in, and a good enlarged image can be obtained.

Furthermore, when the television receiver of the present invention is applied to a television receiver for use as a monitor for measurement, the vertical blanking period of the television signal can be changed by turning on switch 8 in FIG. In addition to being able to display images on the screen, by turning on the switch 23fr, parts including the blanking period can be enlarged and displayed, such as the state of track switching on a video recorder or images from a color television camera. It is possible to measure the state of superposition of the three colors of the signal.

Furthermore, in the circuit described above, switches 16, 18, 23 and 31 can also be implemented using electronic switches.

Also, NAND circuit 30VC. By arbitrarily changing the supplied signal, it is also possible to enlarge and display portions other than the blanking period. Furthermore, the screen division is VC as mentioned above.
．． Not limited to dividing into 4, binary counters 10 and 1
2nd place can be changed arbitrarily Vc. Therefore, various divisions can be performed.

The present invention can also be applied to horizontal deflection circuits.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an embodiment of a television receiver according to the present invention, and FIGS. 2 to 6 are waveform diagrams for explaining the same. 1 is an input terminal to which a television signal is supplied; 2 is a synchronous separation circuit; 3, 5, 8 and 24 are monostable multivibrators, respectively; 4, 9, 13, 15, 20, 22 and 2
5 is an inverter, 6 and 7 are trigger circuits, 10 and 12 are binary counters, and 11
14, 19, 28 and 29 are flip-flop circuits, and 16, 18, 23 and 3 are respectively flip-flop circuits.
1 is a switch, 17 is a buffer/amplifier, 21
and 30 are NAND circuits, 26 is a synchronous pulse amplifier, 27 and 33 are output terminals, and 32 is a blanking circuit.

Claims (1)

[Claims] 1. A deflection signal forming circuit that forms a horizontal or vertical deflection signal with a frequency n times the reference horizontal or vertical deflection frequency (n>1), and a cathode ray tube in which the output signal of the deflection signal forming circuit is supplied to the deflection means. and a blanking circuit that blanks the video signal in a horizontal or vertical deflection period other than every n-th horizontal or vertical deflection period of the horizontal or vertical deflection signal from the deflection signal forming circuit, A television receiver characterized in that an image of n times the size of a normal screen is displayed by supplying every nth video signal extracted by the blanking circuit to the cathode ray tube.