JPS5912217B2 - Digital Sawtooth Phase Lock Loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital sawtooth phase-locked loop, and more particularly to a seven-point lock loop (PLL) used for high-speed synchronization signal reproduction for burst signals in synchronization signal reproduction circuits and the like.

Generally, when input signals are phase-locked, the stable points of the phase-lock loop system are the two points a and 2 in FIG. 2, and points a and c are unstable points.

Conventionally, the sensitivity characteristic of the phase shifter used in this system is a sine waveform.

Therefore, when the initial phase is near A or C, it takes a considerable amount of time until the phase shifts to the stable point of A or C, which is impractical and inconvenient in reproducing high-speed synchronization signals.

For this purpose, a sawtooth waved phase-locked loop as shown in FIG. 1a is conventionally used.

As shown in Figure 1a, this consists of a first phase shifter 1, a second phase shifter 2, an Okiwave device 3 connected to the phase shifter 1, a voltage controlled oscillator 4 connected to it, and a voltage controlled oscillator 4 connected to the oscillator 4. 9 phase shifter 5 and 180° phase shifter 6, and oscillators 4 and 1
8^ Includes a switch 7 connected to the phase shifter 6 and controlling the phase shifter 1 with its output, and a comparator 8 connected to the 90° phase shifter 5 and the phase shifter 2 and whose output is supplied to the switch 7. Consists of.

In the phase-locked loop system configured in this way, the output waveforms of phase shifter 1 and phase shifter 2 are shown in Fig. 2a.
and b, and the input signal at this time is close to the oscillation frequency of the voltage controlled oscillator.

In other words, the output of phase shifter 2 is 90% relative to the output of phase shifter 1.
When the output waveform of phase shifter 2 is on the positive side, the output wave of phase shifter 1 remains unchanged, and the output waveform of phase shifter 1 is changed only when the output waveform of phase shifter 2 is on the negative side. By inverting , a sawtooth waveform as shown in FIG. 2d can be obtained at the output of the phase shifter 1.

This allows the retraction phase range of the phaser to be ±180° compared to the conventional one.
The angle becomes ±90°, which means that the retracting time is at most η times as long.

180° of phase-locked loop with sawtooth wave
As the phase shifter 6 and the phase shifter 5, those shown in FIG. 1c have been used.

However, the oscillation frequency of the 90° phase shifter 5 shown in Fig. 1C is not constant, and the phase does not always shift by 90°.The sawtooth waveform is often asymmetrical and is extremely unstable. It was not very practical because the control voltage was controlled by alternating current.

An object of the present invention is to make the phase shifter and switch in the conventional sawtooth phase-locked loop digital, and to configure the phase shifter and switch in a stable and non-adjustable circuit.

According to the present invention, an input signal whose phase should be locked is received, and a signal whose phase is delayed by 90 degrees from the input signal is generated,
A phase lock in which a sawtooth wave having stable points at two points in one cycle of the input signal, that is, a positive slope side and a negative slope side of the input signal, is created by the signal, and the input signal is locked by the sawtooth wave. In the loop,
a voltage-controlled generator in which the means for generating the 90-degree phase delayed signal generates a frequency four times that of the input signal; and a first frequency divider that divides the output of the voltage-controlled generator by two; A second and third frequency divider divides the output of the first frequency divider and its inverted output by two, and reset signals of the second and third frequency dividers are switched to obtain a 90° phase difference. A digital sawtooth phase-locked loop is proposed, characterized in that it comprises means for obtaining a signal having the following characteristics:

Embodiments of the digital sawtooth phase-locked loop according to the present invention will be described in detail below with reference to the drawings.

As shown in FIG. 3, the phase-locked loop system according to the present invention includes phase shifters 11 and 12 to which an input signal is applied, a filter 13 connected to the phase shifter 11, and a filter 13 connected to the waveform filter 13. a voltage controlled oscillator 14 connected to the oscillator 14, a 1/2 frequency divider 15 connected to the oscillator 14, a comparator connected to the phase shifter 12, and whose inputs are connected to the frequency divider 15 and the comparator 16, whose outputs are connected to the phase shifter 12. The device includes a phase shifter and a switching device 17 connected to devices 11 and 12.

In FIG. 3, voltage controlled oscillator 14 oscillates at a frequency four times that of the input signal, and its output is applied to frequency divider 15 and phase shifter and switch 17.

Here, the circuit of the frequency divider 15 and the phase shifter switch 17 is connected to the fourth circuit.
FIG. 5 shows the waveforms of each part of FIG. 4.

In FIG. 4, the frequency divider 15 is a flip 70 knob 15a.
The Q and 4-terminal outputs are applied to the C input terminals of flip-flops 17a and 17b, respectively.

The Q output terminal of the flip-flop 17a is applied to the phase shifter 11 and also to the input terminal of the gate N7c.

Furthermore, the Q output terminal of the flip-flop 17b is connected to the phase shifter 12.
and is connected to one input terminal of the gate 17d.

On the other hand, the other input of the gate N7c and the gate) 17d
A control signal from the comparator is applied to the inhibit input terminal of gate 17c, and the output of gate 17c is sent to the reset terminal of flip-flop 17b via monomulti 17f.
The output of d is connected to the reset terminal of the flip-flop 17a via a monomulti 17e.

In the circuit configured as described above, first, the oscillation frequency of the voltage controlled oscillator 14 is not made to match the conventional input signal frequency, but is oscillated at a frequency four times the input signal frequency, which is 1/1 as shown in FIG. When the signal frequency-divided by the 2 frequency divider 15 is further divided by 1/2 by the flip 70 knobs 17a and 17b, signal waves each shifted by π/2 can be created.

In this case, phase uncertainty occurs during frequency division, and as shown in FIGS. 5A and 5B, the phase advances or lags by π/2, which must be removed.

To do this, as shown in Fig. 4, the output e of the flip-flop 17b is inputted to the reset input of the flip-flop 17a, and the leading edge of the output e is used as shown in Fig. 4 f to obtain the waveform of the monomulti 17e shown in Fig. 4 f. If this waveform is used as a reset signal for the 7-lip-flop 17a, the waveform e will always be delayed by π/2 compared to the waveform d.

Conversely, if the output e of the 7 lip-flop 17a is used as the reset signal of the 7 lip-flop 17b, the waveform e becomes the waveform d.
Therefore, it will definitely advance by π/2.

This detailed diagram is shown in FIGS. 5A and 5B, and each waveform a to f corresponds to each point a=f of the circuit in FIG. 4.

Therefore, if the phase shifter and switch 17 are controlled using the control signal from the comparator 16 as shown in FIG. 4, it is possible to have exactly the same function as in FIG. 1 described above.

Thus, according to the present invention, the waveforms supplied to the phase shifters 11 and 12 have a phase difference of 90°, and also depending on the oscillation frequency, a perfect sawtooth wave can be obtained, unlike filter type or delay type phase shifters. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional sawtooth phase-locked loop, FIG. 2 is an explanatory diagram of the operation of the blocks in FIG. 1, and FIG. 3 is a block diagram of a sawtooth phase-locked loop according to the present invention. FIG. 4 is a block diagram of the frequency divider and phase shifter/switcher shown in FIG. 3, and FIG. 5 is an explanatory diagram of the operations of the blocks shown in FIGS. 3 and 4. In the figure, 14 is a voltage controlled oscillation, 15 is a frequency divider, and 17 is a phase shifter and a switch.

Claims (1)

[Claims] 1. Receives an input signal whose phase should be locked, generates a delayed signal with a phase of 90 degrees from the input signal, and uses the signal to detect two points in one cycle of the input signal, that is, the positive slope side and the negative slope side of the input signal. In a phase lock loop that creates a sawtooth wave having a stable point on the slope side of the input signal and locks the input signal with the sawtooth wave, the means for generating the signal with a 90 degree phase lag has a frequency four times that of the input signal. a 10th frequency divider that divides the output of the voltage controlled generator by 2; and 2nd and 10th frequency dividers that divide the output of the first frequency divider and its inverted output by 2. 3
A digital sawtooth wave phase-locked loop comprising: a frequency divider; and means for switching reset signals of the second and third frequency dividers to obtain a signal having a phase difference of 90 degrees.