JPS5913032B2 - pitch display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In music education, it is important to accurately teach the pitch (frequency) of vocalizations.

The present invention relates to an interval table and display device used in such cases. For example, as shown in FIG.
Character 11 of ``...'' and character 12 of the floor name ``Do, Re, Mi...'' are displayed horizontally in two lines, and then a semitone Vertical line 0 indicating pitch by interval 1
4 is displayed, and when the user speaks into the microphone, the pitch of the voice is displayed as a bar graph 13 with the vertical axis as the time axis, and a vertical line 14 specifically indicating the pitch is displayed.
This allows fine adjustment of the position in the horizontal direction.

5 An example of the present invention will be described below.It goes without saying that the pitch display device according to the present invention can be used not only for human vocalizations, but also for tuning musical instruments, analyzing noise, and various other applications. However, to simplify the explanation, I will explain using audio as an example.

FIG. 2 is a system diagram showing the overall configuration. The voice of the speaker is converted into an audio signal by the microphone 1, this audio signal is supplied to the filter circuit 100, the fundamental wave component of the audio signal is extracted, and the fundamental wave component of the audio signal is extracted. The wave 5 component is supplied to the detection circuit 200, its frequency is detected (frequency discrimination), and this detection signal is supplied to the conversion circuit 300.

This conversion circuit 300 converts the detection signal from the previous stage into an information signal indicating which octave of the absolute scale the pitch of the fundamental wave component is included in, and which pitch within that octave. . Then, the information signal indicating the pitch and the information signal indicating the octave are stored in the storage circuit 40.
0 and is supplied to the monitor receiver 2 through the video signal forming circuit 500.

In this case, the storage circuit 400 stores the information signal up to the present time, and stores this together with the information signal at the present time.
This is for supplying it to the next stage and displaying the pitch up to that point as shown in FIG.

Furthermore, the receiver 2 performs vertical and horizontal deflection like an ordinary television receiver, and therefore the memory circuit 400
A storage signal (information signal) is converted into a video signal for display on the receiver 2 in the forming circuit 500. Next, let's explain each circuit in detail.

FIG. 3 is a system diagram of a filter circuit 100 that extracts the fundamental wave component of an audio signal. In this figure, 101 is a tracking filter, 102 is an amplifier, and 103 is a rectifier circuit.The tracking filter 101 has a low-pass cutoff characteristic as shown in FIG. is controlled by a signal obtained by rectifying the output signal of the amplifier 102;
When the output of amplifier 1 is large, the cutoff frequency f is low, and amplifier 1
When the output of 02 is small, the C cutoff frequency f is controlled to be high.

Therefore, the fundamental frequency component of the input signal is extracted at a predetermined level to the output side of the amplifier 102, and the harmonic components are blocked by the filter 101. When the frequency of the fundamental wave increases, the amplifier 102 As the output level of the filter 101 becomes smaller, the cutoff frequency of the filter 101 becomes higher, and as the frequency of the fundamental wave becomes lower, the output level of the amplifier 102 becomes larger, so the cutoff frequency of the filter 101 becomes lower, and the amplifier 102 always outputs At a certain level, the fundamental wave component of the input signal is extracted.

FIG. 5 is a circuit example showing a specific connection diagram of the filter portions of the filter 101, amplifier 102, and rectifier circuit 103 shown in FIG.
Capacitors 114, 115, field effect transistor 11
6 and 117 constitute a low-pass filter 101, and the operational amplifier 121 constitutes an amplifier 102 whose gain is determined by resistors 122 and 123.

Then, the output signal of the operational amplifier 121 is transmitted to the diode 13.
1, is supplied to the gates of field effect transistors 116 and 117 through a rectifier circuit 103 consisting of a resistor 132 and a capacitor 133.
The impedance value between the source and drain of filters 16 and 117 is changed, and the cutoff frequency of the filter 101 is controlled. By the way, the fundamental wave component extracted in this way is
When the amplitude changes, a change in phase occurs near the cutoff frequency of the filter 101, resulting in a phase difference with respect to the original signal.

Therefore, in order to remove this phase difference, a logic circuit 105 is provided as shown in FIG.

This logic circuit 105 consists of a JK flip-flop circuit 10 which has a clock terminal that is triggered by the falling edge of an input signal and a clear terminal that is reset by an input voltage of '0'.
6,107, both have the potential of Ebi at the J terminal,
A potential of '0'' is always supplied to the K terminal, and the negative output terminal of the flip-flop circuit 107 is connected to the clear terminal of the flip-flop circuit 106 through a delay circuit 170 of about 200 ns consisting of a resistor 171 and a capacitor 172. The positive output terminal of the circuit 106 is connected to the clear terminal of the flip-flop circuit 107. Furthermore, the output signal of the amplifier 102 is supplied to the clock terminal of the flip-flop circuit 106 through the waveform shaping circuit 104, and the output signal of the microphone 1 is supplied to the clock terminal of the flip-flop circuit 106. It is supplied to the clock terminal of the multivibrator 107 through the waveform shaping circuit 109. Therefore, when the audio signal Sa as shown in FIG. 6A is obtained from the microphone 1, the audio signal Sa as shown in FIG. Output signals Sb such as are extracted, and these are N and B', respectively.
When the signal is waveform-shaped and supplied to the logic circuit 105 as shown in FIG. 6, a signal Sc as shown in FIG. 6C is obtained.

That is, first, at the fall of the waveform-shaped signal Sb'', the flip-flop circuit 106 is inverted, the clearing of the flip-flop circuit 107 is released, and then at the fall of the waveform-shaped signal Sa', the flip-flop circuit 107 is inverted. The signal Sc falls, which causes 2
After 00ns, the flip-flop circuit 106 is cleared, and its output immediately clears the flip-flop circuit 107.
is cleared, and the signal Sc falls to return to the original state. In this way, in this filter circuit 100, a pulse signal having the same frequency and phase as the fundamental wave of the input signal is extracted.

Next, FIG. 7 is a system diagram of the frequency detection circuit 200 and the conversion circuit 300 that converts the frequency into two information signals of a scale and an octave.

In the figure, 207 is a counter, and the signal from the above-mentioned filter 100 is supplied to this counter 207, and the number of cycles of the input signal is counted.

On the other hand, 201 is, for example, a 320kHz oscillator, and this oscillation pulse is supplied to a 1/8 frequency dividing circuit 202,
A kHz clock pulse is generated and is supplied to a counter 205 through a selection circuit 204.

Furthermore, as described later, the contents of the counter 205 are [512].
When the value exceeds 0, the selection circuit 204 is switched to the opposite position as shown in the figure, and the clock pulse whose frequency is divided by 1/2 by the frequency dividing circuit 203 is supplied to the counter 205. Further, the contents of the counter 207 are supplied to the decoder 208, and the contents of the counter 207 are "2n", that is, "1, 2, 4, 8".
At this time, a pulse signal is extracted, and this pulse signal is supplied to the gate circuit 209.

In addition, the output signal of “256” of the counter 205 and [
An output signal of ``512'' is supplied to the OR circuit 211, and the OR gate circuit 209 is kept conductive for a period when the content of the counter 205 is ``256'' or more.

This gate output is then supplied to a monostable multipipelator 210 with an extremely short inversion time of, for example, 500 ns, and the monostable multipipelator 215 is triggered at the trailing edge of the output pulse of this multivibrator 210, and this output pulse is The frequency divider circuit 202 through the OR circuit 214
, and are supplied to counters 205 and 207, and these circuits are cleared.

Further, 213 is a flip-flop circuit, which is set by a signal taken out through a decoder (AND circuit) 212 when the content of the counter 205 reaches "528", and is set by a signal from the filter 100. The light is set.

Then, during the period when this flip-flop circuit 213 is set, the output signal of 2 is supplied to the OR circuit 214, and during this period, the frequency dividing circuit 202, counter 205, 2
07 is cleared. Further, when the content of the counter 207 becomes "9", the output signal is taken out from the decoder 208, this signal is supplied to the OR circuit 214, and the frequency dividing circuit 2
02, counters 205 and 207 are cleared.

Therefore, when a pulse signal is supplied from the filter 100, the flip-flop circuit 213 is reset, the clear state of the frequency divider circuit 202 and counters 205 and 207 is released, and counting is started. And counter 205
When the content of exceeds "256", the gate circuit 209 is made conductive through the OR circuit 211, and when the content of the counter 207 becomes "2n" in this state, the decoder 208
The multivibrator 210 is triggered by the output of
Subsequently, the multivibrator 215 is triggered, and this output pulse causes the frequency dividing circuit 202, the counters 205, 2
07 is cleared.

Thereafter, counting is restarted from "o" and this operation is repeated. In this way, the counter 205 detects the time equivalent to 2n cycles of the input signal, and the counter 207 detects the number of cycles of the input signal required for the above-mentioned detection.
Assuming that the value detected in 05 becomes [x], the frequency corresponding to this "x" requires 1 cycle for detection.
The values are different depending on the period, the case of 2 periods, the case of 4 periods, and the case of 8 periods.

However, in this case, if the time is constant and the number of periods in between is doubled, the frequency is doubled.

On the other hand, when the frequency of the fundamental wave of a signal is doubled, the pitch becomes one octave higher. Therefore, when the above-mentioned "x" is an arbitrary number, the corresponding frequencies are 2n times larger than each other, that is, they are intervals of the same note name in different octaves, and in the counter 205, This note name is detected.In this case, the note name detection is 1
The octave is divided into 256 parts and detected as a position signal in units of 256 parts. On the other hand, in the counter 207,
The number of periods of the input signal is detected, thereby detecting which octave the input signal is included in.

In addition, in this device, when the content of the counter 205 is "512", the lowest frequency detected is the lowest frequency detected by the counter 207.
When the counter 205 counts "1", the frequency in this case is , and the highest frequency is when the counter 205 counts "256" and the counter 207 counts "8". , the frequency in this case is , which is the frequency range of the fundamental wave of voice (80Hz to 1000Hz)
are sufficiently covered.

Therefore, the content of the counter 205 becomes "256",
Before the gate 209 becomes conductive, the counter 207
If the content becomes "8", that is, if the counter 207 counts "9", this clearly means that a sound other than a human voice or a harmonic has been erroneously detected.

Therefore, in the above-mentioned device, the contents of the counter 207 are "
9'', the decoder 208 detects this, clears the frequency dividing circuit 202 and counters 205 and 207, and repeats the detection. Further, in the case of normal detection, there is a time when the input signal always has a period of 2n while the contents of the counter 205 change from "256" to "512".

However, human speech usually has a frequency fluctuation of about ±3% (
vibrato) exists. Therefore, for example, if the 2n-1th period pulse is just before the content of the counter 205 reaches "256", the 2n
The content of the counter 205 is [512] for the pulse of the period.
It may not occur until . Therefore, in the above-mentioned device, the content of the counter 205 exceeds "512" and becomes "16" (as described later, in this case, the selection circuit 204
is switched to the output side of the frequency divider 203, so that counting is continued without being cleared until it reaches "32" (approximately 6% of 512). However, if the content of the counter 205 exceeds "528", it is assumed that the input signal is non-periodic or unstable and cannot be measured, and this is detected by the AND circuit 212 and the flip-flop circuit 213 is set. As a result, the frequency dividing circuit 202 and counters 205 and 207 are cleared. In this case, the input signal is not supplied and "528
'', the flip-flop circuit 213 is set, and the frequency divider circuit 202 and counters 205 and 207 remain in the clear state until the next input signal is supplied and the flip-flop circuit 213 is reset. Note that in normal detection, the content of the counter 205 is "256".
The range from "512" to "512" is detected as one octave, but if the contents of the counter 205 exceeds "512" as described above, the range from "512" to "1024" is detected as one octave.
corresponds to an octave.

In other words, the width of frequency change corresponding to one clock pulse is halved, so in the above device,
When the content of counter 205 exceeds "512", selection circuit 204 is switched off so that the clock pulse supplied to counter 205 is divided in half. The contents of the lower eight digits of the counter 205 thus obtained are supplied to the register 301. In addition, the counter 205
is supplied to the encoder 303 through the selection circuit 302, and the output signal of the encoder 303 is sent to the register 30.
4.

Furthermore, the output signal of the multivibrator 210 described above is supplied to the registers 301 and 304 as a write pulse.

Also, while the flip-flop circuit 213 is set, its output signal is sent to the register 301 as a clear signal.
, 304.

In this case, in the selection circuit 302, the counter 20
The output signals of each digit of ``1, 2, 4, and 8'' of 7 are supplied to one of the switching contacts of the changeover switches 311 to 314, and the output signals of ``2, 4, and 8'' are supplied to each of the digits of 1, 2, 4, and 8. It is supplied to the other switching contacts of the switches 311 to 313 of the lower digit, and the other switching contact of the switch 314 is grounded.

Therefore, when each switch 311 to 314 is switched to the position shown in the figure, the contents of the counter 207 are supplied as is to the encoder 303, and when the switches 311 to 314 are switched to the opposite position as shown in the figure, the contents of the counter 207 are supplied to the encoder 303 as is. The signal is halved and supplied to the encoder 303. Furthermore, this selection circuit 304 is controlled by the output signal "512" of the counter 205, so that during the period when the content of the counter 205 is from "512" to "528", the content of the counter 207 is 1/
2 and is supplied to the encoder 303. Then, the output signal of this encoder 303 is supplied to the register 304, but in this case, as mentioned above, writing to the register 304 is performed when the content of the counter 207 is "2n", so writing to the register 304 is performed. The contents of the counter 207 when the
Therefore, the value of n at this time is binarized by the encoder 303 and supplied to the register 304.

In this case, the contents of the counter 205 range from "512" to "
528'', it means that the counter 205 is counting twice as much as it should have been, so in this case, the selection circuit 303 halves the contents of the counter 207 and then registers. 304.

In this way, the note name data obtained by dividing one octave into 256 from the counter 205 and the octave data from the counter 207 are written to the registers 301 and 304. According to this circuit, the input signal can be measured for 2n cycles. Octave data and pitch data are extracted separately.

Also, since measurements are always performed by counting 256 pulses or more, when the frequency is high and the period is short, the period required for measurement automatically increases, and the average value is taken out, so the timing of the clock pulse for detection is Errors due to this will be reduced.

Furthermore, the output signal of the flip-flop circuit 213 causes
Since registers 301 and 304 are cleared,
When there is no input signal and there is no sound, the register 301
, 304, unnecessary signals are not extracted. Furthermore, FIG. 8 is a system diagram of an example of the memory circuit 400.

In this figure, 401 is a read-only memory, in which the pitch data obtained by dividing one octave into 256 from the register 301, the pitch name data obtained by dividing one octave into 12 for each semitone, and the pitch data obtained by dividing each semitone into 16. In this case, the error data is converted into
An 8-bit input signal is converted into 4-bit pitch name data of 12 types from 0000 to 1011 and 4-bit binary coded error data.

The 8-bit output signal from the read-only memory 401 and the 2-bit octave data from the register 304 are held in the register 450 according to the output signal from the monomulti 215, and are supplied to the random access memory 402. .

Further, the output signal of the flip-flop circuit 213 is supplied to the reset terminal of the register 450 through the OR circuit 451, and its value is reset to "O" when there is no signal.
On the other hand, 403 is a synchronous board, 404 is a counter, and 403 is a synchronous board.
The vertical synchronizing signal from 03 is supplied to the reset terminal of the counter 404, the horizontal synchronizing signal is supplied to the counting terminal,
This counter 404 obtains a signal that increases by 1 in units of horizontal periods for each vertical period.

This signal is supplied to the address terminal of random access memory 402. Furthermore, 405 is a variable frequency oscillator, which generates a pulse signal of, for example, 20 Hz.

This pulse signal is then supplied to a counter 407 through a gate circuit 406, and the counter 407 receives two pulse signals.
A sequentially increasing signal is obtained with a pulse signal of 0 Hz.
The signal from this counter 407 and the counter 40 described above
4 is supplied to a comparison circuit 408, and when they match, an output signal is supplied to an AND circuit 409.

Also, the horizontal synchronization signal from the synchronization board 403 is output to the AND circuit 4.
09, and this AND output is sent to the random access memory 4 as a write pulse through an OR circuit 410.
It is supplied to the write control terminal of 02. Therefore, normally, the contents of the random access memory 402 are sequentially read out every horizontal period, and this reading is repeated every vertical period.

On the other hand, when the contents of the counters 404 and 407 match, a signal is taken out from the comparison circuit 408, this matching signal is taken out for one horizontal period, and a signal is sent from the AND circuit 409 during the horizontal synchronizing signal period, that is, the horizontal blanking period. This signal is supplied to the random access memory 402 as a write pulse through the OR circuit 410, and the contents of the registers 301 and 304 at that time, that is, the data obtained by detecting the pitch of the input signal, are stored in the random access memory 402. It is written to an address determined by the contents of counters 404 and 407. Furthermore, the counter 40
Each time the content of 7 increases by 1, the address written to the random access memory 402 moves in order. In this case, as will be described later, for example, the 16 horizontal periods at the top of the screen are used as the display area for note names and scale names, so 16 is set on the counter 407 to prevent data from being written to this area. Preset.

Further, the output signal of the counter 407 is supplied to the decoder 411, and when the number of horizontal scanning lines used for display on the display surface of the display device described later reaches, for example, 240, the signal is taken out from the decoder 411, and the enable signal of the counter 407 is output. is supplied to the terminal to prevent the counter 407 from counting any further. In addition, the above-mentioned filter 1
An output pulse of 00 is supplied to a triggerable monostable multivibrator 412, and this multivalve generator 41
The gate circuit 406 is controlled by the output signal No. 2, and is rendered conductive while the multivibrator 412 is inverted. Therefore, if there is no input signal for more than the inversion time of the multivibrator 412, for example 1 second, the gate circuit 406 becomes non-conductive, the counter 407 stops counting, and writing to the random access memory 402 is disabled. It will no longer be done. Furthermore, when the input signal is supplied again, the multivibrator 412 is inverted, the gate circuit 406 becomes conductive, the counter 407 restarts counting, and writing to the random access memory 402 is performed again. ,
In this case, the counter 40 at the time writing is resumed
7, the count has been advanced by the number corresponding to the inversion time of the multi-pipe router 412 since the last time the signal was supplied, and during this time, each address of the random access memory 402 contains the input signal. Furthermore, the display control circuit 600 sends a start signal to the register 450 set terminal and the counter 4 through the OR circuit 451.
07 and is also supplied to the OR circuit 410.
is supplied to the write control terminal of the random access memory 402 through.

Therefore, while the counter 404 counts one vertical period,
If the start signal continues to be supplied, "0" is written to each address of the random access memory 402, all data is erased, and data can be written again from address 16 given by the value of the counter 404. Become. In addition, in the above example, since the oscillation frequency of the oscillator 405 is 20 Hz, the contents of the registers 301 and 304 at that time, that is, data regarding the pitch of the input signal, are transferred to the random access memory 402 20 times per second. However, by varying the frequency of the oscillator 405 using a control signal from the display control circuit 600, the number of times this writing is performed can be changed, and the time interval for detecting the pitch of the input signal can be changed.

In this way, the data from registers 301 and 304 is stored in random access memory 402 through register 450, but in this circuit, when there is no input signal, the output signal of oscillator 405 is cut off, Since the contents of the counter 407 do not change, the data at [O] when there is no input signal is repeatedly written to the same address, which prevents unnecessary use of many addresses with such useless data. do not have.

Moreover, in this case, even if there is no input signal, the counter 40 remains
Since the count of 7 continues, the counter 40
Data [0] is written to the address designated by 7, and the space between these is blank, and the part where the input signal is interrupted is displayed. Furthermore, in the circuit described above, the oscillator 405
By changing the oscillation frequency of the input signal, the time interval for writing the pitch of the input signal can be arbitrarily changed.

Furthermore, FIG. 9 is a system diagram of a signal forming circuit 500 that forms a video signal to be displayed on the television receiver 2 from data stored in the random access memory 402.

In this circuit, reference numeral 501 denotes a comparison circuit, and data signals sequentially read out in a horizontal period from the random access memory 402 described above are supplied to one input terminal of the comparison circuit 501.

Further, 502 is a counter, which is composed of, for example, 10 bits, of which the lower 4 bits are a hexadecimal binary counter 521, and the next 4 bits are (0000) to (1).
011)'s hexadecimal counter 522, the upper two bits are 4
Each is configured as a decimal binary counter 523, and these are connected in series.

Further, 503 is a variable frequency oscillator, and this oscillator 503
At this time, a clock pulse of, for example, 7.68 MHz, which is phase-locked by the horizontal synchronization signal from the synchronization board 403, is formed.

Then, this clock pulse is supplied to the counter 502, and this counter 502 is preset to an initial value by the horizontal synchronization signal, and in this counter 502,
For example, assuming that the horizontal effective scanning period of the picture tube 2 is 50 μs,
A horizontal position signal is generated by dividing this into 384 parts.

In this position signal, the lower 4 bits are a binary code, the next 4 bits are a decimal code of (0000) to (1011), and the upper 2 bits are a binary code. This is a signal in the same format as the data signal from random access memory 402 described above, with the lower 4 bits being error data, the next 4 bits being pitch name data for each semitone, and the upper 2 bits being error data.
Bits correspond to octave data. This position signal is supplied to the other input terminal of comparison circuit 501 and compared with the data signal from random access memory 402, and the signal is taken out when the data signal is larger or when they match.

This signal is supplied to an adder circuit 504, where it is combined with blanking pulses, synchronization pulses, etc. from the synchronization board 403, and this combined signal is supplied to the monitor receiver 2. thus,
The color of the scanning line is changed from the scanning start position of the horizontal scanning line on the screen 10 until the data signal and the position signal match.

However, in this case, the unit of the position signal is a value obtained by dividing the scan into 384, and the upper counter 502
When the count of 23 exceeds 2, the color of the scanning line changes over the entire section, and no further display is possible.

In contrast, the data signal from random access memory 402 can take on that value until the upper two bits become 4. Therefore, in the above-mentioned circuit, the display can be shifted by presetting the counter 502 to a predetermined value.

That is, 505 is an up/down counter for setting a preset value, and for example, 3Hz from the oscillator 506.
clock pulses are supplied to the up input terminal and down input terminal of the counter 505 through the gate circuits 507 and 508, and the gate circuit 507 or 508 is arbitrarily made conductive by a control signal from the display control circuit 600. is set to the desired value.

When the counter 502 is reset, this value is preset in the counter 502. Note that this counter 505
is a hexadecimal counter 552 and a quaternary counter 553 connected in series, forming preset values corresponding to counters 522 and 523 of counter 502, respectively.

Therefore, when the clock pulse from the oscillator 503 is supplied to the preset counter 502, the data signal and the position signal match in the comparator circuit 501 earlier by the preset value, and the display is scanned as a whole. Shifted toward the starting position.

Note that when one clock pulse from the oscillator 506 is supplied to the up input terminal of the counter 505, the content of the hexadecimal counter 552 of the counter 505 is incremented by "1".

Therefore, when the contents of counter 505 are preset in counter 502, the display is shifted by one semitone toward the scanning start position. Also, when 12 clock pulses are supplied to the up input terminal of the counter 505, the counter 505
The contents of the quaternary counter 553 are increased by "1" and the display is 1.
It is shifted by an octave toward the scan start position. Further, in this circuit, the oscillation frequency of the oscillator 503 is varied by a signal from the display control circuit 600.

By doing this, for example, when the frequency of the oscillator 503 becomes higher, the counter 502 counts faster and the time until the signals match in the comparison circuit 501 becomes shorter.

On the other hand, since the scanning speed of the horizontal scanning line is constant,
The part where the scanning line changes color on the screen 10 becomes shorter,
As a result, the display contents are reduced, and the display range can be expanded by displaying two or more octaves, for example. Similarly, by lowering the frequency of the oscillator 503, the display can be enlarged to make minute changes clearer. Below, the note names "A, B.C......" will be displayed on the screen 10 of the receiver 2.
”11 and floor name “Do, Re, Mi...”1
2 and a vertical line 14 based on a pitch display signal will be described.

In this case, the note name and scale name are displayed in two rows over 16 horizontal scanning periods at the top of the screen, and the note name corresponds to the frequency, for example, by shifting the display as described above. If you shift the characters, the characters will also be shifted at the same time.
Scale names, on the other hand, can be freely moved through transposition, modulation, etc. Therefore, in this circuit, the hexadecimal counter 531
A counter 512 in which a hexadecimal counter 532 is connected in series, and a hexadecimal up-down counter 513 are provided.

Furthermore, gate circuits 514 and 515 controlled by the display control circuit 600 are provided, and the clock pulses from the oscillator 506 are extracted through the gate circuits 514 and 515, and the extracted clock pulses and the clock pulses from the gate circuits 507 and 508 are combined. is OR circuit 51
6,517 to the counter 513, and the contents of this counter 513 are supplied to the counter 532 of the counter 512.
so that it is preset to However, the counter 512
The lower 4 bits of the counter 531 are normally (000
0) is preset.

Therefore, in this counter 513, the gate circuit 50
7, 508 are made conductive to shift the display data, this counter 513 also counts, the preset value for the counter 512 is changed, and the gate circuits 514, 515 are made conductive. In this case, only the counter 513 counts independently, and only the preset value for the counter 512 is changed.

Note that the counter 513 is a hexadecimal counter and supplies a preset value to the hexadecimal counter 532 of the counter 512.

The contents of the hexadecimal counter 532 of this counter 512,
The content of the hexadecimal counter 522 of the counter 502 is selected by the selection circuit 509, and the character generator 5
10 character selection terminals.

This character generator 510 configures characters with dots in a matrix of, for example, 8 rows and 8 columns, and uses signals supplied to a character selection terminal to generate pitch names such as "A.B.C.
"..." or floor name "Do, Re, Mi..."
. . .'' is formed, and this character signal is repeatedly taken out in sequence for one horizontal scan by the signals of 0 to 7 of the lower three bits of the count output of the horizontal period from the counter 404.

Note that when the same signal as the 4-bit pitch name data when the sound "A" is recorded in the random access memory 402 in this circuit is supplied from the counter 522 of the counter 502 to the character generator 510, the character generator 510 receives [A]. ”
The character signals are extracted, and hereafter "B", "C"...
Make sure that the character signal of ... is extracted.

Furthermore, in this circuit, the character signal is a decimal binary signal for both pitch names and scale names.

Therefore, the character generator 510 is controlled at the same time as the selection circuit 509 is switched, and the counter 50
When the signal from the counter 512 is supplied, a character signal of the note name is generated, and when the signal from the counter 512 is supplied, the character signal of the scale name is generated. The control of the character generator 510 and the switching of the selection circuit 509 are performed according to the contents of the horizontal period counter 404. That is, the contents of the counter 404 are supplied to the decoder 518, and the decoded output is sent to the selection circuit 509 and the character generator. 510, the contents of the counter 502 are supplied to the character generator 510 for the first 8 horizontal scanning periods to form a character signal of the pitch name, and the contents of the counter 512 are supplied to the character generator 510 for the 8 horizontal scanning periods 9 to 16. 510 to form a character signal of the floor name.

Note that, from this character signal, one horizontal scan of each character is extracted in parallel.

Therefore, this parallel signal is loaded into the shift register 511 by a pulse signal for each semitone from the decoder 519, and this shift register 511 is driven by a horizontal position signal from the oscillator 503, so that the signal is taken out serially in the horizontal scanning direction. make it possible to do so. Furthermore, 520 is a gate circuit which controls the screen 10 by a control signal from the decoder 518.
It is made conductive only during the first 16 horizontal scanning periods.

A signal from the shift register 511 is then supplied to the adder circuit 504 through this gate circuit 520. In this way, note names and scale names are displayed in two lines in the range of 16 horizontal scanning lines at the top of the screen 10, but according to this circuit, gate circuits 507 and 508 are rendered conductive. , when the display of data on the screen 10 is shifted, the letters of the pitch name and scale name are also shifted at the same time.

Further, when the gate circuits 514 and 515 are rendered conductive, only the characters of the scale name move, and for example, when transposition, modulation, etc. are performed, the scale name can be displayed in accordance with the tone.

Furthermore, a pulse signal for each semitone from the decoder 519 is supplied to the adding circuit 504.

Therefore, a vertical line 14 is formed on the screen 10 to indicate the position of each semitone. By the way, when a piano or the like is used for lessons, there may be cases where the piano is not perfectly tuned.

In such a case, displaying data by piano sound 13
This means that the characters 12 of the floor name and the vertical lines 14 do not match. That is, for example, even if a "C" sound is played on the piano, the tip of the bar graph 13 due to this sound will not match the position of the "C" according to the scale name letter 12 and vertical line 14 of the interval table. Such discrepancies make it difficult to understand pitches and cause confusion in classes.

Therefore, in the present invention, it is possible to further finely adjust the display position of the vertical line 14, so that the display of the vertical line 14 can be adjusted to the display of data based on this sound based on the pitch of the piano used for class. This is what I did.

That is, 1 corresponding to the counter 531 in FIG.
A hexadecimal up-down counter 540 is provided.

Further, gate circuits 541 and 542 controlled by display control circuit 600 are provided, and clock pulses from oscillator 506 are taken out through gate circuits 541 and 542, and these clock pulses are supplied to counter 540. The contents of this counter 540 are then preset to the hexadecimal counter 531 below the counter 512. According to this, the characters 12 and vertical lines 14 of the floor name are:
It is moved left and right in units of 1/16 semitone intervals.

Since this unit is also the smallest unit for displaying data, for example, it supplies the sound of "C" on a piano and displays the sound at that time, and also controls the gate circuits 541 and 542 to match the data display. 12 letters of floor name and vertical line 14
By moving the display of the data, the display of the floor name characters 12 and the vertical line 14 can be completely matched. Furthermore, when the oscillation frequency of the oscillator 503 is changed as described above, the counting speed of the counter 502 and the counting speed of the counter 512 can also be changed. The spacing between letters and vertical lines between semitones is also expanded or decreased at the same time.

In this way, in the device of the present invention, an interval table with vertical lines attached at semitone intervals is displayed on the television screen 10 along with letters of note names and scale names, and the intervals of the user's voice are displayed here in the form of a bar graph. If the pitch is off, you can see it at a glance, and if the user changes the pitch and pronounces it at the correct pitch, the length of the bar graph will change according to the change in pitch. , which makes it very easy to vocalize at the correct pitch, and can be used to great effect in music education.

Furthermore, according to the present invention, a tracking filter is used as a filter circuit when extracting the fundamental frequency component, and the cutoff frequency is changed using the output signal as a control signal, so that the fundamental frequency component is always at a constant level. The output signal of the filter is then compared with the input signal, and the zero-crossing point of the input signal immediately after the zero-crossing point of the output signal is extracted, so there is no phase shift between the input signal and the output signal. Accurate fundamental waves can be extracted.

In addition, when detecting the frequency value, the time for 2n cycles of the input signal is detected, and the number of cycles (2n) of the input signal required for detection is measured, and from this number of cycles, the input signal is In addition to detecting which octave it belongs to, we also detect which pitch outside that octave from the above-mentioned time, so the octave data and pitch data of the input signal are extracted separately, making subsequent processing easier. . In addition, in the memory circuit, the horizontal synchronization signal is repeatedly counted and used as an address signal.
Since the oscillation signals of the Hz oscillator are counted and data is written when they match, data is written sequentially from the upper scanning line on the screen at intervals of, for example, 1/20 seconds. Since the oscillation frequency of the oscillator can be changed arbitrarily, the data writing interval can be changed arbitrarily. Furthermore, a gate circuit is provided on the output side of the oscillator, and this gate circuit is made non-conductive when there is no input signal, so the write address does not change when there is no input signal, and the address of the random access memory is not wasted.

Furthermore, since this control signal is taken out through a monostable multivibrator, when the input signal disappears, "0" data is recorded for a predetermined period, making the break in the input signal clear.

Furthermore, according to the present invention, pitches are displayed, and characters for pitch names and scale names are displayed, and when the display range is moved, the display of these characters also moves at the same time, making it easier to read the display. becomes easier. Furthermore, since only the letters of the scale name can be moved separately, it is possible to cope with modulation or transposition. In addition, the display position of the scale name letters and vertical lines at semitone intervals can be finely adjusted to match the pitch of the piano being used, so when teaching using a piano, the sound of the piano etc. can be used as a reference. It is possible to carry out classes based on the following information, and there is no need to tune pianos etc. one by one.

Furthermore, since the displayed content can be enlarged or reduced, it is convenient for displaying a wider range or for reading minute changes.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of pitch display according to the present invention, Fig. 2 is a system diagram showing the overall configuration, Fig. 3 is a system diagram of a filter circuit, and Figs. 4 and 6 are for explanation. Figure, 5th
The figure shows a connection diagram of an example of a tracking filter, Figure 7 is a system diagram of an example of a frequency detection circuit, Figure 8 is a system diagram of an example of a memory circuit, and Figure 9 is a system diagram of an example of a video signal forming circuit. be. 1 is a microphone, 100 is a filter, 200 is a frequency detection circuit, 300 is a conversion circuit, 400 is a storage circuit, 50
0 is a video signal forming circuit, 600 is a control circuit, and 2 is a monitor receiver.

Claims (1)

[Claims] 1 detection means for detecting the frequency of the fundamental wave of the input signal;
A conversion circuit that converts this frequency into octave data and pitch data, a storage circuit that stores these data, a data display signal based on these data, letters of note names or scale names, and intervals that display pitch positions for each semitone. and a video signal forming circuit for forming a display signal, and projects an interval chart on the screen of a monitor receiver consisting of letters of pitch names or scale names based on the pitch display signal and a pitch position display for each semitone, In addition to displaying in this pitch table based on the data display signal, the video signal forming circuit uses a high frequency clock pulse related to the horizontal synchronizing signal of the monitor receiver to read out the storage circuit and A pitch display signal is formed, and with respect to the formation of the pitch display signal using this clock pulse, the timing of forming the scale name character signal and the pitch position display signal are changed, and the pitch display signal is changed from the above to the reference pitch data. A pitch display device in which at least the display position of the pitch display on the screen of a monitor receiver can be adjusted to a display based on a data display signal of the pitch serving as the reference pitch.