JPS5913753B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to the generation of pedo effects in electronic musical instruments.

An electronic musical instrument that superimposes a plurality of frequency-divided signals in an octave relationship 20 to generate each note name separately, and extracts a sound source signal corresponding to a key operation or an address signal for reading a waveform memory from this superimposed frequency-divided signal, has been patented. No. 52-105105 (
(see Japanese Patent Application Laid-Open No. 1983-38109) or Japanese Patent Application No. 1983
It is shown in the specification of No. 2-15003925 (see Japanese Patent Laid-Open No. 54-82225).

The present invention makes it possible to generate a pedo sound in the above-mentioned type of electronic musical instrument, that is, an electronic musical instrument that uses a superimposed frequency division signal generation circuit to set the sound source frequency. The present invention will be described in detail below based on an embodiment of the accompanying drawings.

The electronic musical instrument of the present invention shown in FIG. 1 includes a first musical tone generating device 101 and second musical tone generating devices 102 and 35.

The first musical tone generating device 101 generates the tone selected on the keyboard at a regular pitch, but the second musical tone generating device 102 generates the same tone at a pitch slightly shifted from the regular pitch. Musical tone signals generated from both devices 101 and 102 are mixed in a mixing circuit 103, and then sent to a tone circuit 10.
4 and then the sound system 105 is reached. When a sound with a normal pitch and a sound with a slightly different pitch are produced together, a bead corresponding to the pitch difference is generated. The key switch circuit 100 generates a multi-bit key code KC representing a key pressed on the keyboard, and a key-on signal KON (1 bit while a key is being pressed) representing a key press.

The tones (pitch name and octave range) to be generated by the first and second musical tone generators 101 and 102 are specified by the key code KC. The key code KC is a 4-bit note code N, ~N4 that represents the tone, and 3 that represents the octave.
Consists of bit octave codes 01 to 0. 1st
The second musical tone generators 101 and 102 have the same configuration, and include a superimposed frequency division signal generator, 106, 107, note selectors 108, 109, and octave selectors 110, 11.
1, waveform memory 112113, envelope generator 11
She and her husband have a total of 4,115. However, the superimposed frequency division signal generation sections 106 and 107 have different tunings, and the superposition frequency division signal generation section 106 of the first musical tone generation device 101 is tuned to the regular pitch (f), and the second musical tone The superimposed frequency division signal generating section 107 of the generator 102 is tuned to a pitch (f+Δf) that is slightly deviated from the normal pitch (for example, a deviation of about 10 cents). Superimposed frequency division signal generators 106 and 107
are each of the 12 note names C#, D. D#・・・・・・・・・B
．． 12 superimposed frequency division signal generators 10 each corresponding to C
6-1 to 106-12 and 107-1 to 107-1
Consists of 2.

The superimposed frequency-divided signal generators 106-1 to 106-12 and 107-1 to 107-12 are in a relationship in which the highest frequency clock signal corresponding to the note name is successively divided (
Each time the amplitude level of at least the highest frequency divided signal among the plurality of divided signals (having an octave relationship) is inverted, data representing the amplitude level of each divided signal at that time is sequentially output in series. . superimposed frequency division signal generation section 106,
As an example of 107, C in the first musical tone generator 1 old
Details of the superimposed frequency division signal generating section 106-12 regarding the # sound are shown in FIG. In the figure, multi-input type logic circuit elements such as AND circuits and OR circuits are illustrated using the illustration method shown in FIGS. 3a and 3b.

This draws one input line on the input side and draws multiple signal lines orthogonal to this input line. The intersection point between the signal line of the signal to be input to the circuit and the input line is surrounded by a circle. For example, the conditional expression for the AND circuit in Figure 3a is A-B-D-Q, and the conditional expression for the OR circuit in Figure 3b is A-B-D-Q.
+B+C=Q. The delay flip-flop adopts the method shown in FIG. 3c, and although the clock pulses for controlling the input/output timing are not particularly shown, they are all controlled by a common clock pulse. The period of this clock pulse is called one bit time.
The superimposed frequency division signal generation section 106-12 can be roughly divided into a digital oscillation section 14 and a frequency division data creation section 15.

The digital oscillator 14 divides the clock pulse at a desired frequency division ratio to generate a basic pulse signal P of a desired frequency, and the frequency division data generator 15 divides the basic pulse signal P sequentially. Digital data (ie, frequency-divided data) regarding a plurality of frequency-divided signals to be obtained is created. This frequency-divided data is sent out serially via lines 13-12. The digital oscillator 14 is a variable frequency divider circuit, and includes a 7-stage/1-bit shift register 16 in which seven delay flip-flops and an OR circuit are sequentially connected in cascade, and a shift register 16 in the sixth and seventh stages of the shift register 16. AND circuit 17 inputting data A6 and A7;
A NOR circuit 18, an exclusive OR circuit consisting of an AND circuit 17, a NOR circuit 18, and a NOR circuit 19 inputting the basic pulse signal P, and data A from the first stage to the sixth stage of the shift register 16. It includes a maximum length counter (maximum length counter) consisting of a NOR circuit 20 that inputs A6, and an AND circuit 21 that detects when the content of this maximum length counter reaches a preset value. Contains. The output "1" of the AND circuit 21 is transferred from the delay flip-flop 22 and the AND circuit 23 to the OR circuit 24 or the AND circuit 25.
The signal is output as a basic pulse signal P via the OR circuit 24. The maximum length counter is set to an initial state by the basic pulse signal P applied via line 26. Therefore, the maximum length counter consisting of the shift register 16 and the like repeats counting from the initial state every time the basic pulse signal P is applied. The modulo number of the maximum length counter, that is, the oscillation interval of the digital oscillator 14 (or the frequency division ratio of the variable frequency divider circuit) & the input connection state of the ζ AND circuit 21 and the output of this AND circuit 21 are delayed by the flip-flop 2.
It is determined depending on the control whether or not the signal passed through 2 is extracted as the basic pulse signal P. The output data A1 to A7 of each stage of the shift register 16 is input to the AND circuit 21 directly or via an inverter. In the example of FIG. 2, data Al, A, , A5, A6 and A7 are directly input, and data A and A4 are input after being inverted by an inverter. Therefore, the contents of the maximum length counter, that is, the data A1 of the shift register 16
When ~A7 is 6110011r', the input conditions A1, A2, A3, A4, A5, A6, and A7 of the AND circuit 21 are satisfied, and the AND circuit 21 outputs "1".

When the signal on the control line 27 is “1”, the AND circuit 23
is enabled, AND circuit 25 is disabled, and a signal delayed by one bit time via delay flip-flop 22 is selected.

Further, when the signal on the control line 27 is 60'', the AND circuit 23 is inoperative, the AND circuit 25 is enabled, and the output of the AND circuit 21 is selected as is (without delay). The input connection state of the circuit 21 is changed to the maximum length by the pulse signal P on the line 26.
Counting from when the counter was set to its initial state, N clock pulses (not shown) are applied to shift register 16 (
If the signal on the control line 27 is 40#, the basic pulse signal P will be generated at an N-ary interval when the data contents A1 to A7 are detected when added to each delay flip-flop (delayed flip-flop). , if the signal on the control line 27 is 1-ary, the pulse signal P is generated at intervals of N+1-ary. After all, the digital oscillator 14 divides the frequency of the clock pulse for the delay flip-flop to generate the basic pulse signal P, and the frequency division ratio is approximately set by the input connection state of the AND circuit 21. Depending on the signal on control line 27, slight changes are made. The actual oscillation period of the basic pulse signal P obtained by frequency division is the clock pulse period (for example, 1
(around μs). The frequency division data creation section 15 includes a memory register capable of serial shift operation consisting of delay flip-flops FF1 to FF7, a 1-bit adder 28, and a carry output C of the adder 28.

It has a delay flip-flop 29 which delays the signal by one bit time and returns it to the carry input Ci via an OR circuit 30 and an AND circuit 31, so as to perform a serial addition operation. During the serial addition operation, the frequency division data creation section 15 serially shifts the contents of the delay flip-flops FF1 to FF7, and transfers the pulse signal P given from the oscillation section 14 to the least significant bit (delay flip-flop F
bit of F'1). Control of whether to perform a serial addition operation, that is, a shift operation of delay flip-flops FF1 to FF7, or a memory operation is performed by the output of the set-reset type flip-flop 32. When the output of the flip-flop 32 is "1" 5, the signal on the shift line 33 is "11".
, the signal on the memory line 34 becomes "0", and the held data is sequentially shifted from the upper delay flip-flop (FF7) to the lower delay flip-flop (FFl).Then, the output data of the lowest delay flip-flop FFl becomes "0". An adder 28 adds the basic pulse signal P or the carry signal from the delay flip-flop 29;
The result is input to the highest delay flip-flop FF7. When the output of the flip-flop 32 is "0", the signal on the memory line 34 becomes "1", the signal on the shift line 33 becomes "10", and the delay flip-flop F
Possession data of Fl to FF7 is self-maintained. Flip-flop 32 produces a set output "11" only for a bit time corresponding to the number of stages of the register consisting of delay flip-flops FF1 to FF7.
To explain with reference to the figure, when one basic pulse signal P is generated from the oscillator 14 at time slot t1 as shown in FIG. 4a, the flip-flop 32 is set via the OR circuit 35. At this time, the shift register 16
The signal "1" is read into the second to seventh stages through the line 26, and the signal "01" is read into the first stage through the line 26 and the NOR circuit 19, so the timestamp after one bit time is In lot T2, data A1 to A7 are 10111 as shown in FIG. 4b.
It becomes 11F'. Since this data is sequentially shifted to the right, data A1 to A7 change as shown in FIG.
At time slot T8 after the bit time, the data A7 of the seventh stage of the shift register 16 falls to 100. This data A7 is inverted via the inverter 36 as shown in FIG. 4c and applied to the reset input R of the flip-flop 32. Therefore, as shown in FIG. 4d, the flip-flop 32 operates for 7 bit times (time slots t1 to t1) from the time when the basic pulse signal P rises to "1".
It is set only during T7) and produces a set output of "1".The signal 1C applied to the OR circuit 35 is "1" when the power is turned on.
This is an initial clear signal that becomes 1. Memory status (
The data held by each delay flip-flop FFl to FF7 when the memory line 34 is "1" is represented by Q1 to Q7, and the data output from the delay flip-flop FF1 in the shift state (shift line 33 is "1") is shown below. The result will be as shown in Figure 4e. That is, during the time slots t1 to T7, the delay flip-flop FFl
From then on, data held in registers FFl to FF7 Q1 to Q7
are output serially from the lowest to lowest. The output of this delay flip-flop FFl is the AND circuit 37 and the OR circuit 38.
is applied to the addition input A of the adder 28 via the addition input A of the adder 28. To explain the serial addition operation, first, at time slot t1, the basic pulse signal P is input to the OR circuit 30 and the AND circuit 31.
It is added to the addition input Ci of the adder 28 via. The AND circuit 31 is enabled to operate from time slot t1 to time slot T7 by the signal "1" on the shift line 33.
In this time slot T, the least significant bit data Q1 from the delay flip-flop FFl is applied to the adder 28, so that the pulse signal P and the least significant bit data Q1 are added to the adder 28.
is added. The addition result (this is referred to as Q/) is inputted from the output terminal S to the delay flip-flop FF7, and the carry output C at that time. is the delay flip-flop 29
join. In the next time slot T2, the pulse signal P disappears, but the carry signal from the lower bit temporarily held in the delay flip-flop 29 is applied to the addition input Ci.
and is added to data Q2. Thereafter, the carry signal from the addition result of the lower bits and the data Q3 to Q7 of the upper bits are sequentially added, and the serial addition ends at time slot T7. At the end of this time slot T8, the output of the flip-flop 32 becomes "0" and the memory line 34 becomes 111, so that the addition results performed from time slots T to T7 are self-held in each delay flip-flop FF1 to FF7. Therefore, the weights of data Q1 to Q7 held by each delay flip-flop FFl to FF7 in the memory state are 21 for FF1, 22 for FF2, and 22 for pulse signal P.
3 is 23, FF4 is 24, FF5 is 25, FF6 is 26
, FF7 is 27. As a result, the basic pulse signal P is frequency-divided into a plurality of stages by the serial addition in the frequency-divided data creation section 15. Their frequency division ratios correspond to the above weights. The frequency-divided data Q, to Q7 created as described above in the frequency-divided data creation section 15 are outputted in series via the line 39, the OR circuit 40, and the AND circuit 41. The AND circuit 41 is enabled to operate only during time slots T and T7 in FIG. 4 by the output of the flip-flop 32, and the frequency-divided data is output only during this period. That is, the output data Q1 to Q7 of the delay flip-flop FFl, which occurs as shown in FIG. be done. Since the aforementioned serial addition operation is performed after the delay flip-flop FF1, the divided data Q, .about.Q7 outputted via line 39 represents the previous serial addition result. By the way, in the time slot t1, the basic pulse signal P is sent to the OR circuit 40 and the AND circuit 4.
1 to lines 13-12. This basic pulse signal P is always 6r'' in time slot t1.
Therefore, the frequency-divided data Q1 is given priority and the data Q is canceled. Therefore, the superimposed frequency division signal generation section 106-12
The content of the data sent to lines 13-12 from
It will look like Figure f. That is, by serializing the frequency-divided data Q, to Q7, the frequency-divided signals are effectively superimposed. It represents the time slot in which the frequency-divided signal superimposed on the basic pulse signal P appearing at the head of the frequency-divided data Q2 to Q7 is located. In the example shown in FIG. 2, slight switching changes in the generation intervals of the basic pulse signals P are made in a fixed combination while four pulse signals P are generated. This combination is determined depending on the setting position of the switch 42. The switch 42 has four terminals Bl, B2, B3,
B4, and the grounded terminal B1 is not given the signal "1" even once while the four basic pulse signals P are given. The lowest frequency divided data Q1 is inputted, and the signal "1" is applied twice while the four basic pulse signals P are applied. Frequency division data Q held in delay flip-flops FFl and FF2
1 and Q2 are applied to an AND circuit 43 and an OR circuit 44, the output of the AND circuit 43 is applied to terminal B3, and the output of the OR circuit 44 is applied to terminal B4. Therefore, the signal "1" is supplied to the terminal B3 only once during the generation of four basic pulse signals P. Furthermore, the signal "1" is supplied to the terminal B4 only once while the four basic pulse signals P are generated. ” is given three times. Table 1 shows the relationship between the values of the frequency-divided data Q1 and Q2 of the lower two bits and the values of the signals applied to each terminal B1-B4 of the switch 42.
The output of switch 42 is applied to control line 27 via delay flip-flop 45 to control the frequency division ratio of digital oscillator 14, that is, the generation interval of basic pulse signal P. As mentioned above, when the frequency division ratio set by the AND circuit 21 is N-ary, when the signal on the control line 27 becomes "1", the basic pulse signal P is generated at the N+1-ary frequency division ratio, and the line When the signal of 27 becomes 60'', it is generated with an N-adic frequency division ratio. Therefore, the frequency division ratio for generating the basic pulse signal P in the digital oscillator 14 is such that the switch 42 is connected to the terminal B.
When set to 1, it is always N-ary, but when set to terminal B, N-ary and N+1-ary are repeated, and when set to terminal B3, N-ary is repeated 3 times and then N+1 only once. If it is set to terminal B4, N-base is performed once and then N+1-base is performed three times. In the example of FIG. 2, switch 42 is set at terminal B4.

The input conditions of the AND circuit 21 in the digital oscillator 14 are "A, · A2 · A3 · A4 · A5 · A6 · A
7'', which means that the maximum length counter in the configuration shown in the figure is set to 112 (N-112). In this case, the numbers in FIG. 5a indicate the number of clock pulses included in the generation state of the basic pulse signal P, that is, the frequency division ratio with reference to the clock pulse. As described above, the AND circuit 41 serially outputs the frequency-divided zetas Q2 to Q7 following the basic pulse signal P. FIG. 5b shows this frequency-divided data sequence Dl, D2, D3, which is sent to lines 13-12.
・This shows the state of occurrence. Each frequency division data string D,
, D, , D3......, as shown in Fig. 4f, the frequency divided data Q2 is
~Q7 are included respectively. Since the frequency division data Q2 with the smallest frequency division ratio is obtained by dividing the basic pulse signal P by one, its value increases by "1" every time two reference pulse signals P are generated.
゛ or inverted to “0”. Therefore, the basic pulse signal P
If a frequency-divided data string is generated with a generation period of , then Fig. 5b
As shown in , data strings with the same content are Dl, Dl, D2,
D2......continues twice. Each of the frequency-divided data sequences Dl, D2, D3, . . . may be generated only once, but there is no particular problem even if they occur twice as in this example. Each frequency divided data string Dl, D
2, D3, . . . , frequency-divided data Q2 and Q are extracted and shown in FIGS. 5c and 5d. Table 2 shows changes in the data contents of the frequency-divided data sequences Dl, D2, . . . over a longer period of time. Among the frequency-divided data Q2 to Q7, the frequency-divided data Q2 repeats inversion of "1" and "O" at the fastest cycle.

Therefore, the signal generated based on the frequency-divided data Q2 is the signal with the highest frequency. As is clear from the numbers shown in FIG. 5a, in the example of FIG. 2, the frequency signal obtained based on the divided data Q2 is the clock pulse for driving the delay flip-flop? The frequency is divided. That is, the frequency divider Q2 is the frequency of the basic pulse signal P divided by one, and in this example, the frequency of the clock pulse? After dividing once? This is because four basic pulse signals P are generated by performing frequency division three times. The frequency signals obtained based on the frequency division data Q3, Q4, Q5, Q6, and Q7 are obtained by dividing the highest frequency signal corresponding to the frequency division data Q2 by 1, respectively.
2481632 Therefore, data of a plurality of frequency signals having an octave relationship are generated in a superimposed manner (serially).

The reason why the switch 42 is provided to allow slight changes in the frequency division ratio is so that it is possible to obtain delicate frequency division ratios that cannot be divided by only the maximum length counter using the 7-stage shift register 16. This is because.

That is, if the AND circuit 21 is operated when the maximum length counter is in the Nth order, the switch 42 is activated.
4N base and 4N+ corresponding to the four terminals B1 to B4, respectively.
It is possible to obtain the frequency-divided data Q2 with slightly different frequency division ratios such as 1-base, 4N+2-base, and 4N+3-base. As described above, the frequency division zetas Q2 to Q7 are serially superimposed and output from the superimposed frequency division signal generation units 106-12 every time the basic pulse signal P is generated.

This superimposed divided signal is applied to note selector 108 via lines 13-12. Other pitch names C. B. A#,...
...D#, superimposed frequency division signal generation unit 106 regarding D
-1 to 10611 are also the generation parts 106-1 shown in FIG.
It has the same configuration as 2.

However, in FIG. 2, the superimposed frequency-divided data Q2 to Q7 are shown to be 6 bits to simplify the explanation, but in reality they are 8 bits, which will be expressed as Q1 to Q8. Therefore, each superimposed frequency division signal generation section 106-1 to 106-1 in FIG.
1 sent from 2 to each line 13-1 to 13-12
The set of superimposed (serial) frequency-divided data strings is the basic timing signal P.
Consists of 9 bits of data including For this reason, it goes without saying that the number of stages of the shift register of the frequency-divided data generation section 15 and the shift register 16 of the digital oscillation section 14 increases. In each superimposed frequency division signal generation section 106-1 to 106-12, the input connection state of the AND circuit 21 (FIG. 2) in the digital oscillation section 14 and the frequency division ratio fine adjustment switch 42 (FIG. 2) are controlled. The settings are different for each
Frequency division data Q2 to Q7 corresponding to the musical tone frequency of the regular pitch of each note name C-B are transmitted to lines 13-1 to 13-, respectively.
It is designed so that it can occur superimposed on 12. The input conditions (A1 to A7) of the AND circuit 21 in each generation section 106-1 to 106-12 and the setting position of the switch 42 (
Examples of B, ~B4) are shown in Table 3. In Table 3,
The column N shows the original frequency division ratio obtained by the maximum length counter (shift register 16, etc.) according to the input connection state of the AND circuit 21, and the columns 1, 2, 3, and 4 show the original frequency division ratio obtained by the maximum length counter (shift register 16, etc.).
This shows each frequency division ratio when generating the basic pulse signals P, which differ slightly depending on the setting position of the switch 42. The column Q2 is the sum of the above four frequency division ratios, that is, the part corresponding to the highest frequency among the frequency division data Q2 to Q7 (Q1 to Q8) for each note led to the output lines 13-1 to 13-12. It shows the frequency division ratio of the frequency data Q2 (Q1). Note that the number indicating the frequency division ratio indicates the cycle of the frequency division signal when the cycle of the clock pulse for driving the shift registers is set to 1.

For example, if the period of this clock pulse is approximately 1 μs, the period of the frequency signal obtained based on the C tone frequency division data Q2 is approximately 239 μs, and this frequency is approximately 418 μs.
4H7. This is the frequency of the 8-foot C8 tone. Further, the period of the frequency signal obtained based on the frequency division decoupling signal Q2 of the C# sound is approximately 451 μs, and this frequency is approximately 2217H2. This is the frequency of the 8-foot C7# tone. Lines 13-1 to 13-1
The superimposed frequency-divided data Q1 to Q8 of each note name sent to the note selector 108 are applied to the note selector 108.

FIG. 6 shows an example of the note selector 108. A decoder 60 decodes 4-bit note codes N1 to N4 representing the pitch name of the pressed key, and the output of the decoder 60 enables any one AND circuit of the note gate 61 to operate. Superimposed frequency division data supply lines 13-1 to 13-12 corresponding to each note name are input to each AND circuit of the note gate 61 separately, and a single The line (13-1 to 13-12) corresponding to the note name is selected. The output of the note gate 61 is led to the line 13A via the OR circuit 62, and the octave selector 11
Add to 0. The octave selector 110 provides superimposed frequency division data P of the single note name selected by the note selector 108,
Input Ql to Q8, replace it with parallel data, and shift the bit position appropriately according to octave codes 01 to 03.

The octave codes 01 to Q3 are decoded by the decoder 63, and the octave signals 0CI- corresponding to each octave are
0C5 is generated. The superimposed frequency divided zeta P. is supplied from the note selector 108 via line 13A. Ql～Q
8 is a series input/parallel output/series shift type with 9 stages/
The data is manually input to the first stage S1 of the 1-bit shift register 64, and sequentially shifted from the first stage S to the ninth stage S. Therefore, from the output end of each stage of the shift register 64, superimposed frequency divided data P, Ql to Q8
A parallelized signal is obtained. Since the superimposed frequency-divided data is supplied intermittently at every generation timing of the basic pulse signal P, the data parallelized by the shift register 64 is latched by the latch circuit 65 to become a continuous signal. Frequency division data Q, ~Q8 latched in latch circuit 65
are used as address signals ADl to AD6 for reading out the waveforms stored in the waveform memory 112.

The shift register 64 is operated by the same clock pulses as those used in the weight frequency division signal generators 106-1 to 106-12.

The superimposed frequency division data is P, Ql, Q2, Q3, Q4, Q5,
Q6, Q7, and Q8 are read into the shift register 64 in this order. At timing t/, the first basic pulse signal P
is read into the first stage S1 of the shift register 64, and the data contents of each stage S1 to S of the shift register 64 from then until timing T,' are shown in FIG. 7a. The inverted output S1 of the first stage S1 of the shift register 64 and the second to ninth stages S,
The output signals up to are input to the NOR circuit 66.

This NOR circuit 66 is for detecting the basic pulse signal P (that is, for detecting the arrival of frequency-divided data Q1 to Q8). Also, the fifth shift register 64
The outputs from stage S5 to ninth stage S9 are input to AND circuits 67 to 71, respectively. The AND circuits 67-71 convert the bit positions of the frequency-divided data Q1-Q8 parallelized by the shift register 64 into octave signals 0C1-
This is for shifting by an amount corresponding to 0C5. After this shift control, the parallel frequency-divided data Q1 to Q8 are latched into the latch circuit 65. The octave signals 0C, to 0C5 output from the decoder 63 are input to AND circuits 67 to 71 in order from the higher octave signal 0C5.

In this case, among the octave signals 0C1 to 0C5, only those corresponding to the octave range of the pressed key are ``1'', so a single octave signal (COL) can be ``1''.
A single AND circuit (67~) corresponding to one of ~CO5)
only one of the 11) becomes operational. Then, the AND circuit (one of 67 to 71) is operable.
When the basic pulse signal P is shifted to the stage (one of S5 to S9) corresponding to the stage (one of S5 to S9), the AND circuit (one of 67 to 71) operates, and the OR circuit 72 sends the signal is added. The arrival of the superimposed frequency-divided data Q1 to Q8 to the shift register 64 is detected as follows.

Since the frequency-divided data Q1 to Q8 are always sent out after the basic pulse signal P, the signal does not appear (is "0") for at least 8 bit times immediately before the basic pulse signal P appears. Therefore, when the basic timing signal P is read into the first stage S1 of the shift register 64, the second stage S representing the signal state of the immediately preceding 8-bit time is read.
The outputs of the second to ninth stages S are all "0".
This time is shown as timing Tl5 in FIG. By reading the basic timing signal P into the first stage S1 of the shift register 114, the inverted output g1 of the first stage S becomes "O".The NOR circuit 66 has the first stage inverted output S1 and Since the outputs from the second stage S2 to the ninth stage S9 are input, an output "1" is generated at timing t/. The output 11' of the NOR circuit 66 is applied to the set input S of the set-reset type flip-flop 73.

This causes the flip-flop 7 to open as shown in FIG. 7b.
3 is in the set state, and the set-side output signal is delayed by one bit time in the delay flip-flop 74 as shown in FIG. 7c, and then applied to the AND circuit 75. thus,
AND circuit 75 is set to an operable state. The outputs of the aforementioned AND circuits 67 to 71 are applied to other inputs of an AND circuit 74 via an OR circuit 72, and also applied to a reset input R of a flip-flop 73.

Since the basic pulse signal P always precedes the frequency-divided data Q1 to Q8, the first reset signal is applied to the flip-flop 73 when the output 1F' is generated from the AND circuits 67 to 71 based on the basic pulse signal P. , the flip-flop 73 is reset. At the same time, the condition of the AND circuit 75 is satisfied, and the output of the AND circuit 75 is applied to the strobe terminal s of the latch circuit 65. When the flip-flop 73 is reset, the output of the delay flip-flop 73 becomes "0" after one bit time. ”,
Even if the output "F" is generated from the OR circuit 72 after that, the AND circuit 75 does not operate.Therefore, the strobe pulse STP applied from the AND circuit 75 to the latch circuit 65 is generated only for one bit time.This strobe pulse ST
The timing at which P occurs is the octave signal 0C1 to 0C5
Determined by.

For example, octave signal 0C5 representing the highest octave
is "F", when the basic timing signal P reaches the fifth stage S5 of the shift register 64, the AND circuit 6
7 operates, and a strobe pulse STP is generated at timing T5' (FIG. 7d). At this time, stages Sl, S2, S3, and S4 of the shift register 64 contain frequency-divided data Q4, Q3, Q2, and Ql (see FIG. 7a). Therefore, these frequency divided data Q4, Q3, Q2, Q
l is read into the latch circuit 65. The latch circuit 65 has six latch positions L1 to L6, and the outputs of the first stage S1 to the sixth stage S6 of the shift register 64 are input to the latch positions L1 to L6 of the latch circuit 65.

The output of each latch position L1 to L6 of the latch circuit 65 is AD
6, AD5, AD42 AD3, AD2, ADl.
AD6 is the most significant bit and AD1 is the least significant bit.
Every time the superimposed frequency-divided data Q1 to Q3 arrive at the octave selector 110 together with the basic pulse signal P, a strobe pulse STP is generated and the memory of the latch circuit 65 is rewritten.

The values of the output signals AD6-ADl of the latch circuit 65 change each time the logical value of each frequency-divided data Q1-Q8 changes. In this way, the latch circuit 65 outputs binary signals AD6 to ADl in which the divided zetas Q1 to Q8 are maintained in parallel and the bit positions thereof are shifted according to the octave signals 0C1 to 0C5.
is obtained. Note that when the octave signal 0C4 is "1", the AND circuit 68 becomes operational, and the timing T6''
(FIG. 7), the strobe pulse STP is generated.

Timing T7 when octave signal 0C3 is 1F''
',0c1 is 8'', timing T8',0c,
When is "1", each strobe pulse STP is generated at timing T9'. The waveform memory 112 stores a plurality of musical sound waveforms, and the timbre selection switch 116
(FIG. 1), a tone waveform corresponding to the selected timbre is selected, and sample point amplitudes of the selected tone waveform are repeatedly read out in sequence in accordance with address signals AD1-AD6. The envelope generator 114 is capable of generating an envelope waveform having a shape corresponding to the timbre selected by the timbre selection switch 116, and is capable of generating an envelope waveform having a shape corresponding to the timbre selected by the timbre selection switch 116.
The envelope waveform signal is generated based on N,
The amplitude envelope of the musical waveform signal read out from the waveform memory 112 is suppressed. The superimposed frequency division signal generating sections 107-1 to 107-12 in the second musical tone generating device 102 have substantially the same configuration as that in FIG. 2. However, the input connection mode of the AND circuit 21 in the digital oscillator 14 is different from that of the first musical tone generating device 101, that is, the superimposed frequency divided signal generating sections 106-1 to 106-12 tuned at regular pitches. It is somewhat different. In this way, by making the frequency division ratio of the digital oscillator 14, that is, the variable frequency divider circuit, somewhat different from the regular pitch, the superimposed frequency divided signal generators 107-1 to 107-12 corresponding to each note name can be tuned to a pitch that is slightly off from the normal pitch. For example, if you want to shift the pitch by +10 cents, the frequency ratio corresponding to +10 cents is 1.
0058, the value obtained by multiplying the frequency division ratio (for example, shown in Table 3) of the superimposed frequency division signal generation units 106-1 to 106-12 corresponding to the regular pitch by the above value (1.0058) The frequency division signal generation units 107-1 to 107-
The frequency division ratio is set to 12.

Also, if you want to shift -10 cents, since the frequency ratio corresponding to -10 cents is 0.9942, the value obtained by multiplying the frequency division ratio of the regular pitch by 0.9942 is superimposed on the frequency division signal generator 107-1. The frequency division ratio is set to 107-12. By the way, in order to change the bead frequency according to the timbre, the timbre selection signals TSl to TSn by the timbre selection switch 116 are used.
The superimposed frequency division signal generation section 10 of the second musical tone generation device 102
7-1 to 107-12, . It is preferable to switch the frequency division ratio of the superimposed frequency division signal according to the tone color.

To do this, for example, as shown in FIG. 8, an AND for frequency division ratio setting in the digital oscillation section 14 (see FIG. 2) in each superimposed frequency division signal generation section 107 (107-1 to 107-12) is required. The circuit 21 (see FIG. 2) is configured with a ROM (abbreviation for read-only memory) 210, and this ROM
It is preferable that the address of 2lO is selected by the tone color selection signals TSl to TSn.

ROM2lO is the output A, ~A7 of the shift register 16.
A plurality of AND circuits 21A to 21A to which each input is inputted in a different manner (in a manner that a pitch shift corresponding to each tone occurs).
21N, and timbre selection signals TS1 to TSn are separately input to each AND circuit 21A to 21N. Therefore, one AND circuit (any one of 21A to 21N) corresponds to the tone selected by the tone selection switch 116.
becomes operational, and the signal P is output from the digital oscillator 14 according to the frequency division ratio corresponding to the input connection mode of the anode circuit.
is oscillated.

Incidentally, the output of ROM2lO is output from the AND circuit 21 in FIG.
Similarly to the output of , it is input to delay flip-flop 22 and AND circuit 25 . In the second musical tone generator 102, a note selector 109, an octave selector 11
1. The waveform memory 113 and envelope generator 115 are:
It has the same configuration as the first musical tone generator 101 and operates in the same manner.

Although the above embodiment has been described as a monophonic instrument, the present invention can also be applied to a compound musical instrument.

For example, from the note selectors 108, 109 in the first and second musical tone generators 101, 102 to the waveform memory 112,
, 113 may be provided for each sound generation channel. In addition, 6 from C1 to C6 (or C2 to C7)
In the case of an electronic musical instrument with one key, one octave is C#,
D. D#・・・・・・・・・B. When classified according to the range of C, the lowest octave consists of only one note, the lowest note C1 (or C2).

Increasing the processing octave by one just for this one note is wasteful. Therefore, regarding the lowest note C, the frequency division signal generator 1 superimposes the frequency division data that is originally one octave lower.
It is possible that this occurs from 06-1 and 107-1. For this purpose, it is preferable to change the configuration of each superimposed frequency division signal generation section 106-1 to 106-12 and 107-1 to 107-12 as shown in FIG. That is, a delay flip-flop 11 is inserted in line 39 (see FIG. 2) to delay the frequency-divided data Q1 to Q7 by one bit time.
Then, the frequency-divided data appearing on line 1312 are P, Q
1 to Q6. In addition, for the lowest note C1 (or C2), C note superimposed frequency division signal generation units 106-1 and 107-
1 is further changed as shown in FIG. In other words, an AND circuit 41' and an OR circuit 40' are added, and an OR circuit 45' is added.
The signal on line 39 is input without delay. Then,
The original output line 13-1 of the C tone contains frequency division data P,Q.
l~Q6 appears or the output line CL for the lowest note C1
Frequency division data P, Q2 to Q7 appear. In the octave selector 110, the octave of the lowest note C1 is C
It is processed as the same octave as the octave of 1# to C2. In this way, since the frequency division data Q2 to Q7 of the line CL for the lowest note C is originally one octave lower than the others (Q1 to Q6), the lowest note C can be obtained in the correct octave range. In addition, in the embodiment shown in FIG.
Waveform memories 112 and 113 are created by parallelizing the superimposed frequency-divided data.
However, the present invention is not limited to this, and the superimposed frequency-divided data may be parallelized and one or more of them may be combined to be used as an analog sound source signal (square wave or staircase wave).

As described above, according to the present invention, a bead effect can be realized in an electronic musical instrument using a superimposed frequency-divided signal generator.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed circuit diagram showing the C# sound as part 1 of the superimposed frequency division signal generating section of FIG. 1, and FIG. 3 is a circuit diagram. 4 is a timing chart illustrating the operation of FIG. 2, and FIG. 5 is a diagram showing a plurality of frequency-divided data serially superimposed from the superimposed frequency-divided signal generator shown in FIG. 2. 6 is a block diagram showing an example of the note selector and octave selector shown in FIG. 1, FIG. 7 is an explanatory diagram of the operation of the octave selector shown in FIG. Figure 2 is a circuit diagram showing a modified part of the superimposed frequency division signal generation section, Figure 9 is a circuit diagram showing another modified part, and Figure 10 is a circuit diagram showing another modified part. FIG. 101...First musical tone generator (with regular pitch), 102...Second musical tone generator (with shifted pitch), 106, 107 (106-1 to 106-1)
2,107-1 to 107-12)...Superimposed frequency division signal generation section.

Claims (1)

[Claims] 1. A variable frequency divider circuit that divides a predetermined clock pulse at an arbitrary frequency division ratio, and a variable frequency divider circuit that sequentially divides the output pulses of the variable frequency divider circuit by 1/1.
a sound source oscillator section having a superimposed frequency division signal generation section for each note name, which consists of a frequency division data creation section that divides the frequency by 2 and serializes the output of each frequency division stage and sends it out; and the superposition frequency division signal generation section. It includes a circuit that selects serial frequency division data for each note name from the section according to the pressed key, and a circuit that parallelizes and latches the selected serial frequency division data, and based on the latched frequency division data. It is equipped with two lines of musical tone generators that generate musical tone signals, and the first
The frequency division ratio of the variable frequency divider circuit in the second musical tone generator is set to a value corresponding to the regular bit of each note name, and the frequency division ratio of the variable frequency divider circuit in the second musical tone generator is set to a value corresponding to the regular bit of each note name. An electronic musical instrument in which a beat is generated between the sounds generated by both musical tone generators by setting values corresponding to pitches that are slightly different from the normal pitch. 2. The variable frequency divider circuit consists of a maximum length counter driven by a predetermined clock pulse, and a circuit that generates a pulse when the value of the counter reaches a preset value to return the counter to its initial state. , the frequency division data creation comprises a circuit that counts pulses generated for each of the preset values, and a circuit that serially outputs the counting result every time the pulse is generated. Electronic musical instruments listed in section. 3. The variable frequency dividing circuit in the second musical tone generating device has a plurality of numerical values corresponding to different frequency division ratios set in advance, and one of the numerical values corresponds to the timbre selected for the generated sound. a maximum length counter driven by a predetermined clock pulse; and generating a pulse when the value of the counter reaches a value selected by the storage circuit, and returning the counter to an initial state. An electronic musical instrument according to claim 1, comprising a circuit for returning the .