JPS5913768B2 - Channel transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel transfer control method, particularly in a system in which a control device such as a communication control device is connected via a multiplexer and transmits and receives data in a burst mode. The present invention relates to a channel transfer control method in which the number of data bytes to be transferred can be variably set according to the state and/or scale of the system, and an optimum through foot can be determined.

A message-buffered controller, such as a communication controller, is connected to the multiplexer channel and
A relatively large amount of data is sent and received via the channel.

This type of control device is generally a block multiplexer.
It is often connected to a byte multiplexer channel, but if the system scale is small or high throughput is not required, it is often connected to a byte multiplexer channel. In the latter case, the above control device and multiplexer
Regarding data transfer between channels, it is necessary to determine the optimal throughput based on the following conditions. That is, ^
Transfer capability of multiplexer channel MXC, (2)
C) the degree of channel occupancy by other input/output devices connected to the multiplexer channel; C) the maximum allowable hold time for the other input/output devices; the throughput conditions required by the device, such as a communication control device; It is necessary to determine the optimal throughput based on the following factors.

In general, when transmitting and receiving data to and from a multiplexer channel, it is preferable from the viewpoint of throughput to transfer multiple bytes in local bursts. However, if other input/output devices are connected to the multiplexer channel and there is a possibility that the input/output devices will cause an overrun, it is necessary to shorten the channel hold time based on the local burst. The present invention aims to solve the above points, and the channel transfer control method of the present invention is such that the control device is connected to a host data processing device via a byte multiplexer channel, and the control device is connected to a host data processing device via a byte multiplexer channel. The number of transfer bytes of multiple bytes of data is set in the data transfer counter to the above-mentioned byte multiplexer channel in burst mode, and the data is sent and received while being decremented every time one byte is transferred. The control device is configured to access the memory in the control device one or more times in order to transfer the plurality of bytes of data. - A feature is that the maximum value of the data transfer time for each transmission/reception in the mode is determined based on the contents of the counter.

This will be explained below with reference to the drawings. FIG. 1 shows an embodiment of a system to which the present invention is applied, and FIG. 2 shows a configuration of an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a communication leg unit, 2 a multiplexer channel, CPU a host data processing unit, 3 a line scanning unit, 4 a central control unit, and 5 a memory for transmitting/receiving communication leg programs. 6 is a channel adapter that stores data, and is a multiplexer.
It shows what controls data transfer between channel 2 and memory 5.

Further, in FIG. 2, numerals 4, 5, and 6 correspond to those in FIG. 1, and 7 is a cycle steal address register for the channel adapter 6 to access the memory 5 by cycle stealing. 8 is a data buffer register in which the transfer data between the multiplexer channel 2 and the memory 5 is temporarily held; 9 is a data transfer counter for the transfer data; Something that counts the number of bytes of
10 is an operational in latch which maintains the communication route between the communication control device 1 and the multiplexer channel 2 while the latch is in the set state; 11 and 12 are access count counters; together make up a quaternary counter, 13 is the burst
The mode transfer number setting units 14, 15, and 16 represent AND circuits, respectively, and the AND circuits 17, 18, and 19 represent OR circuits, respectively.
For example, from the communication control device 1 to the host data processing device CP
When transferring data to the U side, as is well known, the operational latch 10 is set to secure the communication route between the multiplexer channel 2 and the communication control device 1, and the channel adapter 6 is set to the address register. 7
According to the contents of , a read z access is performed to the memory 5 by cycle stealing. As a result, in the case shown in the figure, 2 bytes of data are read out from the memory 5 side at a time, and are passed through the OR circuit 17 to the data buffer register 8.
is set to Then, each byte is transferred to the host data processing device side via the channel bus in. When the 1 byte worth of transfer is performed, the contents of the counter 9 are incremented by 1. That is, the number of bytes equal to the number of transfer bytes set in advance in the counter 9 can be finally transferred. When 2 bytes of data are read onto data buffer register 8 as described above, the contents of address register 7 are incremented by 2, and read access to memory 5 is performed again by cycle stealing. Conversely, when data is transferred from the host data processing device CPU side to the communication control device 1 side, the operational in latch 10 is still set, and the channel
By bus out, data is transferred one byte at a time from the host data processing unit CPU side and set in the data buffer register 8.

At this time, in order to manage the data so that a predetermined number of bytes can be finally transferred, the counter 9
The content of is decreased by -1. The data set in data buffer register 8 performs write access to memory 5 according to the contents of cycle steal address register 7. Then, each 2 bytes are stored at a predetermined location in the memory 5. Of course, the data is sent to the line side. Data transfer between the communication control device 1 and the host data processing device CPU side is processed as described above, but as stated at the beginning of this specification, in order to improve throughput, burst mode is used. It is desirable to carry out a data transfer, during which operational latch 10 is kept set and multiplexer channel 2 is occupied for communications controller 1.

Therefore, if another input/output device is connected to the multiplexer channel 2, data transfer between the other input/output device and the host data processing device is prohibited. Therefore, in some cases, an overrun occurs on the side of the other input/output device. In the case of the present invention, when data is transferred in the burst mode, the time during which the multiplexer channel 2 is occupied can be set in accordance with the aspect of the system. In the illustrated case, a configuration is shown in which a 2-byte burst or an 8-byte burst can be selected. For example, whether to select a 2-byte burst or a combination of 8-byte bursts is determined on the condition that no system overrun occurs; in the case shown in FIG. When a burst instruction is given in advance, OR circuit 19 is kept on. When performing an 8-byte burst, memory 5 is
is accessed once, the access count counters 11 and 12 are reset, and each time the channel adapter 6 accesses the memory 5, the AND circuit 14 is reset.
A clock is supplied to the access number counters 11 and 12 via.

In the case shown, when memory access is performed four times,
AND circuit 15 is turned on. Under this condition, the data buffer register 8 and the host. Data transfer between the data processing device and the 2-byte section (
When the operation (twice for one byte) is completed, the AND circuit 16 is turned on and the operational in latch 10 is reset. That is, the possession of the multiplexer channel 2 by the communication control device 1 is temporarily released, and data transfer by other input/output devices is allowed. Of course, above 8
If the illustrated "2-byte burst instruction" signal is set to logic "1" during data transfer by byte burst, the AND circuit 16 is turned on and the operational in latch 10 is reset. Therefore, when performing data transfer by 2-byte burst as necessary, it is sufficient to set the illustrated "2-byte burst instruction" signal to logic "1". Note that the configuration of the burst mode transfer count setting unit 13 is not limited to the one shown in the figure, and may be configured to instruct bursts of any number of bytes by manual setting or program setting. be. As described above, according to the present invention, the occupation time of a multiplexer channel by burst mode transfer can be arbitrarily set in accordance with the aspect of the system.

Therefore, the risk of causing an undesired overrun can be prevented.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a system to which the present invention is applied, and FIG. 2 shows a configuration of an embodiment of the present invention. In the figure, 1 is a communications pedestal, 2 is a multiplexer channel, CPU is a host data processing unit, 4 is a central pedestal, 5 is a memory, 6 is a channel adapter, and 7 is a cycle steal address register. , 8 is a data buffer register, 9 is a data transfer counter, 10 is an operational in latch, 11 and 12 are access count counters, and 13 is a burst mode transfer count setting unit.

Claims (1)

[Claims] 1 connected to a host data processing device via a byte multiplexer channel, and a control device transmits the number of bytes of multiple bytes of data to the byte multiplexer channel in burst mode. In a control device configured to send and receive data by setting it in a transfer counter and decrementing one byte every time it is transferred, and to access the memory in the control device once or multiple times in order to perform the sending and receiving, An access counter is provided to count the number of times the memory is accessed when transferring the multiple bytes of data, and the maximum value of the data transfer time for each transmission/reception in the burst mode is determined based on the contents of the counter. A channel transfer control method characterized by being configured to.