JPS5914826B2 - Buffer memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory system, and more particularly, to a buffer memory control method that prevents block data fetched from main memory immediately before being replaced when data is replaced. Regarding the method.

Conventional set-associative buffer memory controls the buffer memory address by dividing it into a "set address," which corresponds to the lower part of the access address, and a "block address," which is unrelated to the access address. The replacement unit controls this "block address". When copying data from the main memory to the buffer memory (this is called a block fetch), one set address corresponding to the access address is determined.

One set address has a plurality of blocks, and one block among these blocks is the part to be replaced in one block fetch.

The replace unit selects one of the plurality of blocks and specifies the location where the data is to be replaced.

If a block fetch is now being performed and all the blocks at the corresponding set address already contain data and there is no empty block, then the replacement part will retrieve all the data in the blocks in the past. Check the oldness of the access, and specify the head address of the block containing the oldest data as the block to be replaced. It is well known that this is called the LRU method. It is already known how to control the replacement switching control bits and the bits written to the replacement memory array each time the buffer memory is accessed.

In the case of control using the complete LRU method, if there are n data blocks corresponding to one set address part, the replace part has (n-1) data blocks for one set address part.
).

/2 suppression bits are held in the phrase memory. One bit of these indicates the ordering of two data blocks among the n blocks, and one set of all bits completely indicates the arrangement, or ordering, of the n data blocks. .

If the buffer memory is now accessed, a set address is determined from the access address, and (n-1)n/2 bits of the phrase memory corresponding to the set are selected as targets for suppression. Upon notification of which data block has been accessed, (n-1) bits are selected and written so that the access order of that data block is the latest. This is a replacement update. By repeating this operation, the phrase memory always stores the order of recentness, ie, oldest, of the accesses of the n data blocks for all set addresses.

Since the set address is determined from the access address at the time of block fetch, this (n
-1) n/2 bits of information, ie information indicating the order of staleness of accesses of all n data blocks, are read.

The logic for extracting the block address of the oldest accessed data block from among these is the opposite logic to that for updating.
Corresponding to each block address, information of n-1 bits out of (n-1)n/2 bits of replacement information is assigned, and the write pattern at the time of update is completely reversed, that is, all bits are inverted. If the pattern is the oldest one, that block is the oldest accessed data block. Therefore, if we use the logic to determine whether or not the n-1 bits assigned to each block correspond to this oldest pattern, one of the blocks is bound to correspond.

The above is the function of the conventional replacement control bit.
Now, when performing a block fetch, in the conventional method, in the process of writing the program fetched r-data into the buffer memory, the contents of the phrase memory array are also rewritten at the same time, thereby registering that the block address was the most recently accessed. ing.

This registration is called a replace update, and this is the timing towards the end of the block fetch access. In spite of this, replacement reading is performed as soon as block fetch access is started, and the position of the block in which data should be replaced is stored in advance.

Therefore, when block fetch accesses are issued consecutively, the address of the replacement data block specified by the first access and the block address specified by the second access are... The same address will be specified unless the contents of the phrase memory are updated. In other words, the exact same location is subject to swapping, and the first block data brought from main memory will be immediately replaced by the second block data, even though there is a strong possibility that it will be used again later. It will be overprinted and erased.

That is, the conventional control system has a drawback in that when block fetches having access addresses indicating the same set address are issued consecutively, the first block data is immediately erased from the buffer memory. In addition, to avoid this, there is a method of waiting for a block fetch to the same set address until the previous block fetch is completed, that is, until the contents of the replace memory are updated and the next block to be replaced can be correctly determined. However, in this case, it was unavoidable that the performance would deteriorate due to the waiting time.

The purpose of the present invention is to replace not only the oldest data block in the case of consecutive accesses of block fetches with the same set address, but also the replacement of the oldest data block in the case of the second access.
By specifying the address of the oldest or nth data block as the replacement target, you can make the second and subsequent accesses wait until the first access is completed, or cause the previously fetched block data to be written repeatedly. The purpose is to solve the disadvantage of being erased by twisting and to improve performance.

In other words, if a next block fetch is required for the same set address before the contents of the phrase memory are updated as a result of a block fetch, if a block fetch is currently in progress and as a result an attempt is made to write the data in main memory. The purpose of this method is to improve performance by not specifying the current block position as the write destination block for the next block fetch.

In order to achieve the above object, the present invention updates the contents of the phrase memory every time the buffer memory is accessed to record that the program containing the accessed data is the latest, and to update the contents of the phrase memory every time the buffer memory is accessed. If it does not exist in the buffer memory, determine the program number to be evicted based on the read data of the replacement memory,
A buffer memory control method for transferring new data from the main memory to a block position corresponding to the block number includes block number storage means for storing the block number of the buffer memory into which the block data is to be loaded during the process of block transfer; A replacement information modification means is provided for modifying the data read from the replacement memory based on the contents of the number storage means, so that when block transfers from the main memory to the buffer memory overlap, the load destination program number in the subsequent block transfer is being processed in advance. The present invention is characterized in that the block number is determined to be different from the load destination block number in block transfer. The concept of the buffer memory system according to the present invention will be explained below.

There has been a conventional idea that if a buffer memory malfunctions, the data block should be made unusable.

This is called delete. As for replacement information, when performing a block fetch, block addresses that have become unusable (in other words, deleted block addresses) should not be specified as the area to be replaced. In this case, the bit pattern of the replacement information assigned to each proc is fixed so that it appears as if that proc has been accessed the latest or near the latest, and a circuit that determines the oldest proc (this is called an LRU circuit) is configured so that deleted blocks are never specified. The replacement information bit fixing circuit for this deletion (this is called a delete circuit) can be placed in the write circuit of the replacement memory and fixed to the stored information, but it can also be placed in the read circuit and then It is also possible to connect an LRU circuit.

The delete circuit is located in the read section of the replacement memory, and the L
If the RU circuit is followed by the same LR circuit, there is no need to create a special logic circuit to determine the second oldest data block.
The second oldest data block can be determined using the U circuit and the delete circuit. This is because once the oldest block is determined and a block fetch is started, the block is made to appear to have been deleted until the block fetch is completed and the contents of the replace memory are rewritten. This is because if it is fixed so that it can be seen, it is the second oldest block that is output from the LRU circuit.

By providing a number of registers for holding results at the output of the LRU circuit, it is possible to similarly output results up to the nth oldest result.

(The nth oldest here means what the phrase pit represents, and if it is not a complete LRU, it is not necessarily the true nth.) For example, a register that holds the result of the LRU circuit and indicates the replacement position of the block fetched data. When three blocks are provided, in a normal block fetch, the oldest block is selected and held in one register.

The other two registers will not be used unless there is another block fetch after this block fetch is completed and the replacement memory is updated.

If the next block fetch with the same set address is issued before the first block fetch is completed, the information read from the replacement memory will be transferred to the oldest data block retained by the delete circuit as the replacement location for the first block fetch. The position is qualified as delete information and removed from the output of the LRU circuit. Therefore, if there are no other blocks to be deleted, L
The second oldest data block is output from the RU circuit and held in the second register.

If a similar block fetch occurs before the first block fetch completes, the oldest and second oldest blocks are deleted and LRUed in exactly the same way.
The output of the circuit is the position of the third oldest block, which is held in the third register.

The above is a case of three registers, but in principle there are two or more registers, up to the number of programs in one set of buffer memory, or the number of program fetches that can be issued between the start and completion of one program fetch. may be provided.

By the way, the problem here is whether a switching signal is required to determine whether or not to delete the block position obtained from the replace circuit in the previous block fetch when block fetches occur consecutively.

Since the purpose of the present invention is to prevent data loss due to successive block fetches having the same set address, a match output signal from a circuit that compares whether consecutive block fetches have the same set address is used. Therefore, pseudo-delete seems to be the most desirable method, but if there is a relatively large number of blocks in one set of buffer memory, that is, a relatively large number of blocks that can be read simultaneously as associative memory, the oldest data should be replaced, or the second oldest data should be replaced. It does not seem that there is much effect on performance depending on whether data is replaced.

Therefore, regardless of the output signal of the comparator circuit as described above, when a continuous block fetch is performed, even if the block position to be replaced in the previous block fetch is deleted, it does not seem to have much effect, and control is easy. In that case,? Of course, it is possible that the set addresses of consecutive block fetches are not the same, but the block position prepared by the previous block fetch corresponds to the set address read out during the previous block fetch, or the oldest block position indicated by the bit in the phrase memory In the latter case, it is the location of the oldest data indicated by another replacement information corresponding to another set address.

Therefore, unless both specify the same block location, subsequent block fetches specify the location of the oldest data at that set address.

Furthermore, even if the same block position happens to contain the oldest data, it will not have much of an effect since only the location of the second oldest data is specified.
Whether or not to always utilize the delete circuit as described above depends on the case.

Furthermore, the LRU circuit is often not necessarily a complete LRU, and various combinations can be considered, such as where in the replacement section the delete circuit is placed. In any case, the present invention merely adds a function to the conventional LRU circuit to determine the oldest data block. This prevents the memory area from being designated as a replacement area, that is, prevents the block fetch data from disappearing immediately, thereby improving coverage. Next, the present invention will be explained with reference to the drawings.

The figure shows a replaceable circuit according to an embodiment of the present invention. In the figure, 1 is a replace memory array, 2 is a replace memory update circuit, 3 is an LRU circuit, 4 is a delete circuit, 5 is a first register, and 6 is a replace memory circuit. is the second register, 7 is the nth register, 8 is a delete block instruction information line, 9 is an access block instruction information line, 10 is an information line that specifies the buffer memory write block number of the first block fetch data, 11 is an information line that specifies the buffer memory write block number for the second block fetch data, 12 is an information line that specifies the buffer memory write block number for the nth block fetch data, and 13 to 15 are AND circuits. , 16 is a control line indicating that the first block fetch is in progress, 17 is a control line indicating that the second block fetch is in progress, and 18 is a control line indicating that the nth block fetch is in progress. be. Normally, based on the replacement information read from the replacement memory array 1, the LRU circuit 3 determines the block of the oldest data and stores it in the first register 5 as the block address at the time of block fetch.

On the other hand, when the use of a specific block is prohibited due to a buffer memory failure, etc., a delete block is instructed by the delete block instruction information line 8, and the replacement information read from the phrase memory array 1 is modified by the delete circuit 4. The deleted proc is made to appear as the latest proc. When successive block fetches are issued, the block address of the first block fetch that has not yet been completed is stored in the first register 5.

Then, at the second block bench, the block number in the first register 5 is input to the delete circuit 4 through the AND circuit 13, and the block number in the first register 5 is excluded from the target of the replacement block. .
Therefore, the block containing the second oldest data is determined by the LRU circuit 3 as the oldest block,
The block number is held in the second register 6 and becomes the write block address for the second block fetch data. Thereafter, when further block fetches continue in the same manner, the block addresses in the (1-1)th block fetches that have not yet been completed are input to the delete circuit 4, and the blocks in question are removed from the target of the replacement block.

Therefore, in the i-th consecutive block fetch, the block containing the i-th oldest data is determined by the LRU circuit 3 as the oldest block, and its block number is held in the first register, and the block containing the i-th oldest data is determined by the LRU circuit 3. This is the write block address for fetch data.

This prevents the same block position in the buffer memory from being designated consecutively as a location for storing data from the main memory during overlapping block transfers.

As already explained, the present invention adds a circuit to the conventional circuit to determine the second or nth (older) data block based on replacement information, so that the same area can be buffered during consecutive block fetches of the same set address. Since the block fetch data is prevented from being designated as an embedded block and the block fetch data is prevented from being lost, this has the excellent advantage of improving performance and simplifying control.

[Brief explanation of the drawing]

The figure shows a replacement circuit according to an embodiment of the present invention.

Claims (1)

[Claims] 1 Every time the buffer memory is accessed, the contents of the replacement memory are updated to record that the block containing the accessed data is the latest, and if the required data does not exist in the buffer memory, the replacement memory is read. In a buffer memory control method that determines the block number to be evicted based on the data and transfers new data from main memory to the block position of the block number, the buffer memory to which the block data is to be loaded is Block number storage means for storing a block number; and contents of the block number storage means when the replace memory for the next block transfer is read before the contents of the replace memory are updated based on the block transfer. A replacement information modification means is provided for modifying data read from the replacement memory based on the following. When block transfers from the main memory to the buffer memory are consecutive, the load destination block number in the subsequent block transfer is the same as the load destination block number in the block transfer during the preceding processing. A buffer memory control method characterized in that a block number different from a previous block number is determined.