JPS5915221B2 - frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency synthesizer suitable for a local oscillation circuit of a superheterodyne receiver, and particularly to a frequency synthesizer suitable for FM band reception.

Recently, with the advancement of digital technology, the local oscillation circuit of the receiver has been changed to a phase-locked loop (PLL) as shown in Figure 1.
A so-called synthesizer receiver, which is composed of a frequency synthesizer consisting of several frequency synthesizers and is designed to improve reception performance, has been put into practical use.

That is, by changing the division ratio N of the programmable frequency divider 2 constituting the PLL 1, the local oscillation frequency fo is generated from the voltage controlled oscillator 3 in steps of the reference frequency fr, and the reference frequency oscillator 4 is replaced by a crystal oscillator. With this configuration, the local oscillation frequency fo can be obtained with the precision of a crystal oscillator, so that reception performance is further improved.

In reality, the reference frequency fr is set to the inter-office frequency of the reception band, and by changing the division ratio N of the programmable frequency divider 2 by 1, the local oscillation frequency fo can be obtained in inter-office frequency steps and tuned. has been done.

In addition, when the local oscillation frequency fo cannot be tracked by the Takato programmable frequency divider 2, such as in the case of the FM band, the same frequency is applied to the front stage of the programmable frequency divider 2 and the output of the reference frequency oscillator 4, as shown in FIG. A frequency divider with a frequency ratio P is a so-called prescaler width.

By the way, if we take the FM band as an example, the inter-station frequency is generally 1.
00 KHz or 200 KHz, but in Europe there are stations that deviate from these inter-station frequencies, so if the reference frequency fr is set to 100 KHz, stations below that frequency will be unreceivable. Become.

If you try to receive all of these stations, you will need to lower the reference frequency and select stations in narrow frequency steps between stations.

However, lowering the reference frequency fr is not preferable because the reference frequency input to the phase comparator 7 will be significantly lowered.

That is, for example, when selecting a station with an inter-station frequency step of 25 KHz, the reference frequency fr is set to 25 KHz, but if the dividing ratio of Brisquera-5 and 6 is set to 10, the reference frequency fr is input to the phase comparator 7. Reference frequency fr' is 2.5KHz
As a result, the time interval for phase control in the phase comparator 7 is 10 times longer than when comparing at 25 KHz, and the fluctuation of the output voltage in the low-pass filter 8 becomes large, which reduces the accuracy of the PLL loop system. As it decreases, the SN ratio also deteriorates.

Also, if the reference frequency is lowered to receive all stations, the division ratio N set in the programmable frequency divider 2 will become a value that does not correspond to the reception frequency or local oscillation frequency.
This makes it difficult to digitally display the received frequency.

For example, the reception frequency range is 88, 0 MHz to 108.0
If we take the upper heterodyne FM band as an example with an intermediate frequency of 10.7 MHz, the local oscillation frequency fo will be 98.7 MHz to 118.7 MHz, but if the reference frequency fr is set to 100 KHz. , the frequency division ratio N is 987 to 1187, which corresponds to the local oscillation frequency fo, so when displaying the reception frequency, it is N-107.
The received frequency can be easily displayed using the subtraction operation.

However, when the reference frequency fr is 25 KHz, the division ratio N is 3948 to 4748, which is not a one-to-one correspondence as described above, so when displaying the reception frequency, N
The operation of X25-107 must be performed.

This NX25 calculation is performed by a microprocessor in the control circuit.
In the case where the control is performed using the above, many processing steps are required, the processing time becomes long, and it becomes difficult to perform the display while simultaneously performing the channel selection operation.

Therefore, the present invention has been made in view of these points, and by applying pulse swallow technology, there is no need to divide the reference frequency even when a prescaler is used before the programmable frequency divider. The present invention provides a frequency synthesizer that can receive stations and easily display received frequencies.

The pulse swallow synthesizer technology applied to the present invention will now be explained.

Figure 3 shows the standard configuration of a pulse swallow synthesizer.
This system is characterized by the configuration of a variable frequency division ratio prescaler 9 whose frequency division ratio is variable and two programmable frequency dividers 10 and 11.

That is, when the PLL is synchronized, the oscillation frequency fo of the voltage controlled oscillator 3 is generally given the relationship of fo = N - f r = (1), where N is the division ratio of the programmable frequency divider and fr is the reference frequency. Here, N is Briskeller's frequency division ratio P, and the frequency division ratios of the two programmable frequency dividers 10 and 11 are A and B, respectively, and N=A+B -P... (2)
Then, by further transforming the formula, N=A+B -P+A-P-A-P -A(P+1)+(B-A) P...
(3), the oscillation frequency f of the voltage controlled oscillator is f
o-(A(P+1)+(B-A)P)f r...
...(4) It is expressed as.

That is, the frequency division ratio of the brisker 9 is configured to be variable between P and P+1, first, the frequency division ratio of the prescaler 9 is set to P+1, and after A frequency division by one programmable frequency divider 10, the frequency division of the brisker 9 is changed. It can be seen that if the ratio is changed to P and the other programmable frequency divider 11 performs B-A frequency division, it is possible to compare the phases for each reference frequency fr even with one Briskeller system.

To explain with a specific example, for example, the reference frequency fr is 100K.
When oscillating a local oscillation frequency of 99.5 MHz in Hz, the required frequency division ratio N is 95'' from equation (1). , i.e., 15'', and set the other programmable frequency divider 11 to the 10th and 100th values of the frequency division ratio, i.e., 99.
and set the frequency division ratio of the prescaler 9 to 10 and 11.

First, the frequency division ratio of the brisker 9 is switched to 11 and the frequency is divided by 5 using one of the programmable frequency dividers 10, and then the prescaler 9 is switched to the frequency division of 10 and the frequency is divided by 94.The overall frequency division ratio becomes 11X5+94X10=995. The voltage controlled oscillator 3 oscillates at a frequency of 99.5 MHz.

In this way, according to the pulse swallow technology, there is no need to divide the reference frequency fr even though it is a brisket type, and since local oscillation frequency data can be set in the programmable frequency dividers 10 and 11, there is no display. This makes it easier.

The present invention focuses on this point, and in other words, the reception frequency, in other words, the local oscillation frequency fo is the reference inter-office frequency.

This pulse swallow technique is applied even when the frequency is a fraction of "/4fr", such as 99.525 MHz compared to 100 KHz.

By the way, when the reception frequency, that is, the local oscillation frequency, generally has a fraction of -(m, n...integer) with respect to the reference inter-office frequency of 100 KHz, the local oscillation frequency fo is the (4th
) formula, fo-(:A(P+1)+(B-A)P←)X100
(5) It is expressed as m, but - that is, fractional frequency division cannot be easily achieved even with the pulse swallow technique.

Therefore, the present invention was made to make this possible.
By transforming equation (5), 00 fo = (m(A(P+1)+(B-A)P)+n)X
-=((mA+n)(P+1) 00 +(m(B-A)n)P)X -...(5)00 Then, from this formula, the reference frequency is □KHz and P+1
Assuming that frequency division and P frequency division are one frequency division cycle.

It can be seen that it is better to increase the P+1 frequency division by n times in the m frequency division cycle, and conversely decrease the P frequency division by n times.

To explain with a specific example, for example, the local oscillation frequency is 99.52
When receiving a 5 MHz station, i.e. a station with a fraction of '/4f r = 25KHz, -1/4 and n = 1
, m=4, A=5, n=99,
fo is f o-((4X5+1)XI 1+(4(99-5
) -1)XIO')X25
...(6), so the reference frequency fr is set to 25
If the frequency is KHz and one frequency division by 11 and one frequency division by 10 is one frequency division cycle, it is good to configure the frequency division by 11 to be increased by 1 in a 4 frequency division cycle, and the frequency division by 10 to be decreased by 1 in the same frequency division cycle.

Specifically, as shown in FIG. 5, 11 frequency division is performed 6 times the first time and 5 times thereafter, and 10 frequency division is performed 93 times the first time and 94 times from the second time onwards.

Furthermore, in the case of a station where the local oscillation frequency fo is 99.550 MHz, m=4 and n=2, so the 11 frequency division is increased twice in the 4 frequency division cycle, and the 10 frequency division is decreased twice.

That is, in the first and second frequency division cycles, 11 frequency division is performed six times, in the third and fourth frequency division cycles, it is performed five times, and in the first and second
In the frequency division cycle, 10 frequency division is performed 93 times, and the third and fourth
The frequency division cycle is performed 94 times (see FIG. 6).

Next, the configuration of the frequency synthesizer of the present invention that performs such an operation will be explained (see FIG. 4).

3 is a voltage controlled oscillator that generates a local oscillation frequency fo; 9
is the coincidence signal S1. which will be described later. S2 makes the division ratio P and P+1
The output of the voltage controlled oscillator 3 is divided by the Briscaler which is switched to .

12 is a first programmable counter that is composed of a down counter and uses the output of the prescaler 9 as a count input; 13 is a second programmable counter that is also composed of a down counter that uses the output of the prescaler 9 as a count input; The frequency division ratio of the programmable counter 13 is set to the same value by the first programmable counter 12.

14 is a zero detection circuit that detects when the first programmable counter 12 counts down to zero and generates a coincidence signal S1.

15 is a zero detection circuit which detects that the second programmable counter 13 becomes zero and generates a coincidence signal S2.

16 is a match signal S2 in which the numerical value n of the above formula (5) is set.
A third programmable counter 17 is a zero detection circuit of the third programmable counter 16 and generates a coincidence signal S3.

18 is the coincidence signal S2 where the numerical value m of the formula (5) is set.
A fourth programmable counter 19 is a zero detection circuit of the fourth programmable counter 18, which is configured with a down counter that counts down from a numerical value m, and generates a coincidence signal S4.

Note that these first, second, third, and fourth programmable counters 12, 13, 16, 18 and zero detection circuits 14, 15
, 17, and 19 constitute a so-called programmable frequency divider.

20, 21, and 22 are local oscillation frequency data setting means connected in parallel to the first, second, and third programmable counters 12, 13, and 16, and 21 is set with data of the integer part of the local oscillation frequency. , 20 are set with data in the first decimal place, and 22 is further set with a numerical value n, and when the coincidence signal S2 is generated, the data of the setting means 20.21 is set in the first decimal place.
, the preset enable terminals (PE) of the counters 12, 13, 16 are transferred to the second programmable counter 12, 13, and the data of the setting means 22 is transferred to the third programmable counter 16 upon generation of the coincidence signal S4.
), the coincidence signal S2. S4 is connected.

Reference numeral 23 denotes data setting means connected in parallel to the fourth programmable counter 18 and configured to set a numerical value m, and a match is made such that the numerical value m of the setting means 23 is transferred to the fourth programmable counter 18 upon generation of a coincidence signal S4. signal S4
is the preset enable terminal (PE) of counter 18.
It is connected to the.

24 inputs the coincidence signal S1 and outputs a delayed output 81.
’ is a D-flip-flop whose output is AND
Briskeller 9 via gate 25 and OR gate 26
It is connected to a signal terminal for switching the frequency division ratio of P to P.

27 has the match signal S1 connected to one input, and the output is O.
An AND gate connected to the R gate 26 bypasses the D-flip-flop 24 and generates an undelayed match signal S1.
is supplied to the P frequency division signal terminal of the brisketer 9.

Reference numeral 28 denotes a flip-flop whose set output Q is connected to the AND gate 25 and whose reset output Q is connected to the AND gate 27, and which is set when the match signal S4 is generated and reset when the match signal S3 is generated. The D-flip-flop 24 supplies the signal to the P-divided signal terminal of 9.
or directly through the AND gate 27.

29 is a display for displaying the receiving frequency, and setting means 20.
A multiplication circuit 3 that multiplies the output of the subtraction circuit 30 that subtracts 107 from the value of 21 by 25× the value of the setting means 22.
1 output is added.

7 is a phase comparator to which the coincidence signal S4 is applied as a divided output of the oscillation frequency of the voltage controlled oscillator 3 to one input, and the frequency and phase are compared to the reference frequency fr of the reference frequency oscillator 4 connected to the other input. Compare and generate error output.

A low-pass filter 8 converts the error output from the phase comparator 7 into a control voltage for the voltage controlled oscillator 3, and these constitute a PLL.

Next, the operation of the present invention having such a configuration will be explained in the case of FM broadcast reception using the upper heterodyne method with an intermediate frequency of 10.7 MHz.

Here, the normal inter-station frequency is 100 KHz, but in order to be able to receive stations with an inter-station frequency of 25 KHz, the reference frequency fr is set to 25 KHz, and the frequency division ratio of Briskeller-9 is switched to 10 and 11. shall be provided.

First, the operation of receiving an 88.825 MHz station will be explained.

At this time, the local oscillation frequency fo is 99.525 MHz, and the reference frequency fr is 25 KHz, so the programmable frequency divider must divide the frequency by 3981.

Therefore, set 199 "20 to 15" in the data setting means 21, and in 22, the fraction 25KHz is 1/4 of 100KHz.
By corresponding to ``1'' is set, and ``4'' is set to 23.
“ is set.

This data is stored in programmable counters 13 and 13, respectively.
The numbers are preset to 12, 16, and 18, and counting down starts from these values.

At this time, it is assumed that the flip-flop 28 is in a set state, and the frequency division ratio of the brisk scaler 9 is set to 11.

Under such condition settings, the oscillation frequency of the voltage controlled oscillator 3 is first divided by 11 by the prescaler 9, and the oscillation frequency of the voltage controlled oscillator 3 is divided by 11. A pulse is input to the second programmable counter 12.13.

At this time, the first programmable counter 12 has a set value of 5.
When the count is counted down and the frequency is divided by 11 five times by the prescaler 9, it becomes zero, and the zero detection circuit 14 generates a coincidence signal S1, but at this time the flip-flop 28 is in the set state. , coincidence signal S1
is supplied to the brisketer 9 via a D-flip-flop 24, an AND gate 25, and an OR gate 26.

At this time, the coincidence signal S1 is delayed by the D-flip-flop 24, so that the prescaler 9 outputs the coincidence signal S1.
The frequency is not switched to 10 frequency division at the same time as the occurrence of , but there is a delay of one 11 frequency division.

Therefore, 11 frequency division is performed six times.

At this time, 6 pulses are also input to the second programmable counter 13, so that the set value of 199" is counted down by 6 to 93".

Thereafter, the delayed coincidence signal 81' causes the prescaler 9 to
is switched to frequency division by 10, and the second programmable counter 13 is down-counted by 1 by a pulse (CP) generated every time the frequency is divided by 10 by the Briskeller 9.

In other words, frequency division by 10 is performed 93 times.

When the second programmable counter 13 downcounts by 93 and reaches zero, the zero detection circuit 15 generates a coincidence signal S2, which switches the Briscaller 9 to divide by 11 again, and sets the numerical values of the data setting means 20 and 21 to 5. “,
'99'' is preset in the first and second programmable counters 12 and 13.

Also, this coincidence signal S2 is input to the third and fourth programmable counters 16 and 18, so that the third programmable counter 16 counts down from the set value of "1" to zero, and the coincidence signal of the zero detection circuit 17 The flip-flop 28 is reset by S3.

On the other hand, the fourth programmable counter 18 has a set value of 14.
"1" is counted down to 13" (see Figure 5).

The frequency division by 11 and the frequency division by 10 are performed until the coincidence signal S2 is generated in one frequency division cycle.

Next, in the same way as described above, first, the first
The programmable counter 12 is counted down, and when the frequency has been divided by 11 five times, the zero detection circuit 14
When the match signal S1 is generated, the flip-flop 28 is now in the reset state, so the AND gate 27 is opened and the brisket 9 is immediately switched to the 10-frequency division.

At this time, the second programmable counter 13, like the first programmable counter 12, is down-counted by 5" to 94.

Thereafter, the frequency division by 10 is performed 94 times in the same manner as described above, and when the second programmable counter 13 becomes zero, the coincidence signal S2 from the zero detection circuit 15 is generated, and the brisket
is switched to 11 frequency division, and the 1st. The second programmable counters 12 and 13 are set with numerical values "5" and "99" from the setting means 20 and 21.

At this time, the fourth programmable counter 18 is further set to "1".
It is counted down to ``2''.

Thereafter, the frequency division operation described above is repeated two more times until the value of the fourth programmable counter 18 becomes zero.

Therefore, when the fourth programmable counter 18 becomes zero, a coincidence signal S4 is generated from the zero detection circuit 19, and is applied to the phase comparator 7 as the frequency-divided output of the voltage controlled oscillator 3. ．． Setting means 22 for the fourth programmable counter 16.18
, 23 numerical value 11".

ゞ4" is preset.

In this state, the 4-frequency division cycle has been completed and everything has returned to its initial state.

This frequency-divided output is the result of 11 frequency division 6+5X3 times and 10 frequency division 93+94X3 times, that is, a total of 3981 outputs, and the phase and frequency are compared with the reference frequency fr of 25KHz in the phase comparator 7. be done.

Thus, in the 4-division cycle, there is one more 11-division cycle,
This means that the frequency divided by 10 is divided by one less frequency.

Thereafter, the same frequency division cycle is repeated unless the data in the setting means 20, 21, 22 is changed.

At this time, the display 29 shows the setting means 20 and 2 by the subtraction circuit 30.
The value ``1'' corresponding to the intermediate frequency from the value ``995'' of 1
The current reception frequency is 88.825 M by inputting the output 1888'' from which 07'' has been subtracted and the 25×1 multiplication result 25 in the multiplication circuit 31.
Displays that it is Hz.

Next, the case of receiving a station at 88.850 MHz, which is 25 KHz higher, will be explained.

At this time, the local oscillation frequency is 99.550 MHz, so the data setting means 21 is set to ``99'' and 20 is set to 15''. Since the fraction of 50 KHz is expressed as - with respect to 100 KHz, the setter stage 22 is ``4'' is set in the setting means 23 for ``2''.

Therefore, this time the third programmable counter 15
By setting GC% 2'', the flip-flop 28 is reset after the end of the 2 frequency division cycle, so during this time, the D-flip-flop 2 is reset in the same manner as described above.
4 is in effect, and over the 2 frequency division cycle, 11 frequency division is performed 6 times and 10 frequency division is performed 93 times, and in the subsequent division cycle, 11 frequency division is performed 5 times and 10 frequency division is performed 94 times.

That is, in the 4 frequency division cycle, 11 frequency division increases twice and 10 frequency division decreases 2 times, so that the overall frequency division becomes 3982, and the local oscillation frequency becomes 99.550 MHz (see FIG. 6).

At this time, the subtraction circuit 30 performs a subtraction of 995-107", and the multiplication circuit 31 performs a multiplication of 25x2", so that the display 29 displays the reception frequency 88.850.
MHz will be displayed.

Furthermore, in the case of 88.875 MHz, which is 25 KHz higher, by setting 13" in the setting means 22, the 11 frequency division is increased by 3 times and the 10 frequency division is decreased by 3 times in the same manner as described above, resulting in a predetermined frequency division ratio. is obtained, and reception of the 88.875 MHz station is performed.

Furthermore, in the case of 88.900 MHz, which is 25 KHz higher, the local oscillation frequency f becomes 99.600 MHz. By setting, the flip-flop 28 is reset when the coincidence signal S3 is generated, and the AND gate 27 can be opened, and when the coincidence signal S1 is generated at the end of the frequency division by 11, the AND gate 27 is opened.
is opened and Briskeller 9 immediately switches to 10 frequency division.

Therefore, as mentioned above, there is no increase or decrease of frequency by 11 or 10, but 11 frequency division is performed 6 times in 1 frequency division cycle, and 10 frequency division is performed 93 times, resulting in 398 frequency divisions in 4 frequency division cycles.
The frequency is divided by 4 to obtain a local oscillation frequency of 99.600 MHz.

In short, the flip-flop 28 is reset by setting the value of n to 0 for 100'', 1 for 25'', 2 for 150'', and 3 for 175'' using the last two digits of the local oscillation frequency fo. It controls the timing of frequency division and the number of frequency divisions in one frequency division cycle.

As shown in FIG. 7, the setting means 20, 21 consists of a decimal reversible counter and the setting means 22 consists of a quaternary reversible counter. If configured to change, automatic sweeping is possible.

In addition, in the above explanation, the reference frequency fr is m = 4, that is, 1
Although the case of 25 KHz, which is 1/4 of 0.00 KHz, has been described, any reference frequency fr can be applied by changing the setting data of m and changing n from O to (m-1).

For example, if m is set to 2, the reference frequency fr becomes 50 KHz, and by setting n to 0 and 1, the local oscillation frequency fo is oscillated in steps of 50 KHz.

Also, if m is 10, the reference frequency fr is 10 KHz, and by changing n from O to 9 in increments of 1, 10 K
The local oscillation frequency fo is oscillated in Hz steps and reception is performed.

As mentioned above, the frequency synthesizer of the present invention can receive even stations with fractional numbers by improving the pulse swallow technology, and since the data corresponding to the local oscillation frequency can be used as preset data for the frequency divider, the reception frequency display can be changed. It is easy to use and has great practical effects.

[Brief explanation of drawings]

1st. Second. FIG. 3 is a block diagram showing the synthesizer system, FIG. 4 is a block diagram showing the configuration of the present invention, and FIG.
．． 6 is a waveform diagram illustrating the operation of the main part of FIG. 4, and FIG. 7 is a diagram showing another embodiment of the main part of FIG. 4. 1...PLL, 2...Programmable frequency divider, 3...Voltage controlled oscillator, 4...
・Reference frequency oscillator, 7... Phase comparator, 8.
...Reducing filter, 9...Variable division ratio prescaler, 12, 13.16, 1B...1st.
Second. Third. 4th programmable counter, 14,1
5, 17, 19...Zero detection circuit, 20.21.
22, 23... Data setting means, 29...
··display.

Claims (1)

[Claims] 1. Consisting of a phase-locked loop (PLL), with a frequency division ratio of P
A prescaler with a variable division ratio that is switched between +1 and P, a frequency dividing means that alternately switches the frequency division of the prescaler and repeats m times, and while the frequency dividing means repeats m times, P+
1. A frequency synthesizer comprising frequency division increase/decrease means for increasing the 1 frequency division by n times and decreasing the P frequency division by 0 times. 2. The frequency synthesizer according to claim 1, wherein the frequency division increase/decrease means increases/decreases the frequency once every time the frequency divider repeats once.