JPS5916269B2 - Complex integrated circuit light emitting display array - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to visual display devices, and more particularly to a composite integrated circuit light emitting display array using a planar array of semiconductor light emitting devices within a transparent monolithic crystal. In some cases, the light is generated on the back side of the crystal, but is transmitted through the crystal, such that the front five sides of the crystal are visible to a light emitting display array.

In the past, various devices for non-permanent visual display of information have been available. Perhaps one of the most widely used and accepted visual display devices is the cathode ray tube. Although cathode ray tubes are surprisingly used in as many applications as cram schools, they have many inconveniences that will limit their use in many applications in the future. These include the need for high voltages (usually on the order of 15,000 volts or more) and X-ray and radio frequency emissions.
5 Requires shielding to reduce radio frequency interference. Additionally, cathode ray tubes are expensive due to their manufacturing complexity and have relatively short lifetimes requiring periodic replacement. The low light output of cathode ray tube displays requires that care be taken to block bright ambient light from interfering with the readability of the display. Even under ideal conditions, cathode ray tube displays, which are analog in nature, have a resolution that is only about 2% accurate. Additionally, the large size, weight, and non-standard height of cathode ray tubes precludes their use in many environments where space is at a premium and a reliable, reliable construction is required. There is. Another type of display is the so-called plasma discharge (or simply "gas discharge") display, in which a gas between planar electrodes in a gas-filled container is excited by a voltage between the electrodes. emit light.

Such devices require relatively high energizing voltages, are somewhat bulky, and have limited lifetimes. Because of their high energizing voltages, they are not directly compatible with semiconductor circuits of the type used in integrated circuits. These and other displays are available in IEEE Spectrum Vol. ll, black 1, Jan
uaryll974, P. 54 Lapidus,. G
．． “Circuit/System Build
ngBlOcks," and their relative advantages are discussed.

Recently, semiconductor light emitting devices such as LEDs (light emitting diodes) have been developed.

The development of these devices overcame all of the limitations of cathode ray tubes mentioned above and led to the prediction of solid state flat displays, which probably have additional advantages. However, while these light emitting devices are useful for X-Y scanning, the simple X-Y matrix of solid state light emitting devices has a number of drawbacks. One major drawback of X-Y scanning of large arrays with on the order of 500,000 light emitting devices is that high peak currents are required for each short period.

For example, assume a flat display has 100 light emitting devices per inch and 500,000 light emitting devices in a 7" x 7" format. 10 mA of DC current is required for each light emitting device to provide an average display brightness of 1000 lumens per square foot.

For a 50 Hz frame rate, the clock scanning rate must be greater than or equal to 25 MHz.

Under these conditions, the peak current in any light emitting device in the array can be calculated to be 5000A. When the magnitude of the DC current in the light emitting device is reduced by two orders of magnitude, the peak current is approximately 50A. This is unacceptable and presents an almost unsolvable problem given the small conductor cross-sectional areas associated with arrays of the above dimensions, as well as the radio frequency interference of electrical potentials. Among several objects of the invention is such a display that has high contrast, brightness and resolution, yet requires low currents and voltages for operation, so that such potential can be realized. To provide a multi-integrated semiconductor light emitting display array, such an array to provide compact, economical and relatively simple integration of semiconductor light emitting devices using semiconductor circuits for attachment of the light emitting devices. and to provide such arrays that are directly compatible with semiconductor circuits.

These and other objects of the present invention are accomplished by providing a sandwich structure comprising a monolithic array of light emitting devices and a monolithic silicon semiconductor integrated circuit, with multilayer metallization and interconnects sandwiched between the two. achieved.

A monolithic array of light emitting devices includes a single transparent crystal, and light is generated on the backside of the crystal adjacent the interface with the integrated circuit. Since the crystal is transparent, light can be seen from the front of the crystal. The integrated circuit includes an array of memory elements, such as flip-flops, that provide drive current for each light emitting device within the transparent crystal. This combination of memory element and light emitting device allows the addressed light emitting device in the X-Y array to be on more than 90% of the time, which means that the peak current requirements within the light emitting device This means that the current is less than 1.1 times the steady-state current required for the brightness level of . The integrated circuit is mounted on a metal heat sink to provide stiffness and uniform temperature distribution. Other objects and features will be apparent or pointed out below.

Referring to FIG. 1, a composite integrated circuit light emitting display array 10 in accordance with the present invention is illustrated generally as an X-Y matrix of integrated memory circuit elements and solid state light emitting devices.

This X-Y matrix array 10 can be addressed in any known manner. Either serial or parallel format can be used. However, for illustrative purposes, FIG. 1 shows a raster scan address circuit that includes an X counter 11 and a Y counter 12. Both X counter 11 and Y counter 12 are reset to zero by a frame sync pulse applied to terminal 13. A clock with an appropriate pulse repetition rate is supplied to the X counter 11 from terminal 14. Both the X counter 11 and the Y counter 12 can be constructed by using conventional binary counters including a cascade of bistable multivibrators and a suitable decoding network;
As a result, the counters provide only a single output, each corresponding to a particular column or row. Thus, with each clock pulse applied to terminal 14, X-counter 11 provides a single output that advances from column 1 to column n of X-Y matrix array 10 in synchronization with the clock. When the X counter 11 reaches the last n count, it also provides an output to the input of the Y counter 12. Thus, Y counter 12, which selects a row of X-Y matrix array 10, is equal to x counter 1.
Count at a rate of 1/n of 1. Y counter 12 is X
Operating in a similar manner to counter 11, X counter 11
produces a single output that advances from row 1 to row n synchronously with the nth count of . When the cycle of Y counter 12 is completed, it becomes 1.
A frame is constructed. A video signal in the form of a serial binary code synchronized with a clock is applied to a terminal 15 connected to a series of AND gates 16 for each column of the X-Y matrix array 10.

X counter 11 has only one AND gate 1 at any one point in time
6 is energized. The video signal applied to terminal 15 is connected to all AND gates 6, so that the video signal is passed through the activated AND gate corresponding to the column selected by X counter 11. As will be explained in more detail, the matching of the respective row and column outputs from Y counter 12 and AND gate 16 selects a particular memory element and its associated light emitting device within X-Y matrix array 10. . This selection triggers the memory element, which provides current to drive the light emitting device. From the foregoing description, it can be seen that the integrated semiconductor display array according to the present invention
It will be appreciated that it is shown in FIG. 1 as being addressed in a manner similar to a normal TV raster.
In such a system, both the frame synchronization pulse applied to terminal 13 and the clock pulse applied to terminal 14 are obtained directly from the appropriate video signal input in a manner well known to those skilled in the art. However, it is emphasized that the invention is not limited to any particular means for addressing the display array, and that the system shown in FIG. 1 is for illustrative purposes only. For example, one or the other of counters 11 and 12 may be replaced by a register such that binary data is transferred to the array in parallel. This is X or Y
Eliminates scanning in one of the directions, thereby greatly reducing the time required to address the entire array. Other methods of addressing the array will readily occur to those skilled in the art. The addressing scheme shown in FIG. 1 sets selected ones of the memory elements into an X-Y matrix array 10.

In accordance with the principles of the invention, it is also necessary to reset the memory elements within the X-Y matrix 10 after a predetermined time. For example, counters 11 and 1
This is facilitated by a second pair of X and Y counters identical to 2 (not shown for simplicity of the drawing). The second pair of X and Y counters is also reset by the frame sync pulse, but at about 9 in the frame period.
Delayed by a time equal to 0%. Obviously, this second
There is no AND gate inserted between the Y counter of the pair of counters and the XY matrix 10. This is because the purpose of this second pair of counters is to unset, not set, the memory elements in the matrix. A description of this second pair of counters has been omitted to avoid unduly complicating the drawing. A simple schematic diagram for one row of elements in the X-Y matrix 10 is shown in FIG.

In this figure, the light emitting devices are represented by light emitting p-n junction diodes (LEDs) 2011-20ni. Here, the first character of the subscript represents the row of LEDs,
The second character represents the line. Although a light emitting Pn junction diode is shown, any semiconductor light emitting device may be used. Thus, aspects of the invention include not only p-n junction diodes, but also simple semiconductor monodes (such as those used in ZnS electroluminescent panels), and which also emit light. p-j-N, . It also includes complex structures such as p-n-p1 and similarly configured junction semiconductor devices. Each of the light emitting diodes 2011-20ni corresponds to a corresponding memory circuit element, that is, a flip-flop 2111-21.
Connected to ni. Each flip-flop 2111~
21. i has two inputs, one corresponding to its associated column, and in this case one corresponding to the first row. Any flip-flop 2111-2
For 1ni to be set (ie, to transition from the first state to the second state), the pulses on the two input lines or conductors must match. Once set, the flip-flop remains set regardless of the state of either of its two inputs until reset by a clear pulse. The clear pulse clears all flip-flops 2111-21 with a single clear line. It will be appreciated that, although shown as being placed simultaneously into the flip-flops, the flip-flops may be individually reset in the same manner as they are set, if desired. The anodes of the light emitting diodes 2011-20ni are each connected to the supply voltage source VB. In operation, the flip-flops in the display array are scanned in the X and Y directions corresponding to the columns and rows of the array.

This scanning operation requires very little power. The coincidence of the X and Y pulses on a particular flip-flop sets or changes the state of that flip-flop, causing its associated light emitting diode to emit light. An important aspect of the invention is that once set, a flip-flop in the set state (second state) remains set until it is reset to the first state, thereby allowing the flip-flop to remain set for a relatively long time. It consists in passing a current through the light emitting diode over a period of time. This minimizes the peak current required for each LED to reach a certain level of luminance. This is due to the fact that the luminance of an LED or similar is directly proportional to the average current in the diode. By keeping the diode conductive for an extended period of time, the same average current can be achieved with much lower peak current values. In the simple on-off single color display of the present invention, the total display brightness change is V
This can be achieved by controlling the B voltage line.

For some types of single-color displays with neutral colors, the second
Additional memory is required beyond what is shown in the figure, in which case the light emitting diodes are turned on by scanning as described above. However, in order to turn off the light emitting diodes at different times corresponding to the desired gray tone, additional scanning is required to turn off the separate elements. Current digital computer technology can be easily used for this purpose. For on-off multicolor or multicolor halftone displays using the present invention, the electronics associated with the display array are the same as those required for the single color displays described above. FIG. 3 is a detailed schematic diagram of a simple 2×2 matrix of memory elements and light emitting devices suitable for incorporation into an integrated semiconductor array embodying the present invention.

The control circuitry for each memory element and its associated light emitting device is the same within the matrix, and only the circuitry of the memory element and its associated light emitting device shown at the top left of the figure will be described in detail. Each memory element includes a flip-flop having two multi-emitter transistors 31 and 32. Transistors 31 and 32 are cross-connected in the usual manner to form a bistable multivibrator. This cross-connection is in the form of a resistor 33 between the collector of transistor 31 and the base of transistor 32, and a resistor 34 between the base of transistor 31 and the emitter of another transistor 35.
Transistor 35 is connected as an emitter follower, and its base is connected to the collector of transistor 32. Each transistor 31 and 32 has a load resistor 3
6 and 37, respectively, which are connected to the logic control power source VL. transistor 35
The collector of transistor 35 is also connected to a logic control power source, but the emitter of transistor 35 is connected through a load resistor 38 to the base of another drive transistor 39. The transistor 39 has its emitter grounded, like a normal emitter, and its collector connected through a load resistor 40 and a light emitting diode 41 to the voltage source VB. The first emitters of transistors 31 and 32 are both at X.
connected to the column address line, each transistor 3
The second emitters 1 and 32 are connected to the YO row address line. The third emitter of transistor 31 is connected to the D-select line, and the third emitter of transistor 32 is connected to the D-tree select line. The D and D* select lines relate to logic control functions that may be used to clear or reset memory elements within the display array.

Both decoding and memory functions are performed by multi-emitter transistors. X or Y address
If the line is low, the flip-flop remains in its current state. When both the X and Y address lines are high, indicating that a memory element has been selected in a scan operation, the flip-flop remains in its current state unless either the D or D* line is high. keep it. Thus, for example, D*line'' is high and
When the D line is at ground potential, transistor 31 is conducting and transistor 32 is non-conducting, setting the flip-flop. When transistor 32 is non-conducting, a positive potential appears at the base of transistor 35, causing it to conduct and turning transistor 39 on. When transistor 39 is conductive, a conductive path is established to light emitting diode 41, causing it to emit light. While both the D and D* select lines are at ground potential, the flip-flop remains in the set or reset state regardless of the state of the X and Y address lines. The flip-flop is set by a high level appearing on the D select line and a ground potential appearing on the D* select line, thereby causing transistor 32 to become conductive;
Transistor 31 is brought out of conduction. This arrangement of the D and D* selection lines provides complete freedom as to how data updates can be made. For example, random updates can be performed when data changes, all memory elements can be cleared, data can be refreshed in a scanning manner, and so on.
The physical configuration of a monolithic light emitting diode diode array according to the present invention is shown in cross-section in FIG.

The array includes a monolithic array 43 of individual light emitting diodes and a multilayer metallized monolithic silicon integrated circuit (LSI) 44 and a spherical interconnect generally shown as 45 sandwiched between the two. It is a Sanderutsch structure that includes. The LSI silicon circuit containing the array of memory elements is mounted on a metal heat sink 46 to provide tight and uniform temperature distribution. A feature of the present invention is that the light is directed to the p-n
The coupling lies in the fact that it occurs at the adjacent point of the interconnect 45 with the LSI circuit 44.

Thus, for example, if the light emitting diode is used as a semiconductor light emitting device, the crystal of array 43 is preferably pn coupled bulk single crystal GaP, typically shown as the pn coupled region of the diode on the back surface of the crystal. has been done. G
Since the aP crystal is transparent, the light emitted at the p-n junction can be seen from the front, as indicated by the arrows in the drawing. The monolithic array of light emitting devices 43 is P
It is shown deeply etched on the n-coupled side 48 to provide a deep channel, which forms a grid separating each light emitting diode region.

Such an etching grid has two advantages. Firstly,
It provides a reflective system that enhances the light from array 43. Second, the grid effectively reduces optical crosstalk between adjacent elements in the array because of the optical isolation it provides. The channels of grid 48 are conveniently organized on the backside of crystal 43 by individual mesas 50 arranged in rows and columns so that the face of each such mesa is rectangular. Each mesa 50 includes a pn coupling region 47, thus each mesa forming an LED.
A typical p-n junction in such a mesa 50 is shown at 51 in FIG. 5, with a layer or region of n-type conductivity shown at 53 and a thin layer or region of p-type conductivity shown at 55. It has a surface layer or region.

The p-region may be formed by diffusing a dopant, such as zinc, into an epitaxially grown n-type material. Of course, suitable metallization (not shown) or other contact means may be provided to the GaP crystal to provide a energizing potential across the individual bonding regions 47, such as one of the mesas shown as 57. One is that no p-type surface layer is applied to provide electrical interconnection between the memory circuit elements and the crystal body 43.

In each case, all opposite sides of the individual diodes are contacted through the crystal body. Spherical or hemispherical metal contacts 49 connect the multilayer metallization 45 and individual p-n junctions to provide good electrical contact between one side of each light emitting diode and the associated memory element in the LSI circuit. Preferably, it is used between p-layers 55 in region 47. The resulting sandwich architecture and electrical interconnections, referred to as flip-chip arrangements, allow for extremely compact construction of integrated semiconductor display arrays in accordance with the present invention.

In the particular example shown in FIG. 4 of a GaP crystal, a single color (green) display is provided.

However, other colors can also be achieved with this display array. For example, a basic GaP crystal can be diffused with arsenic on the Pn junction side, providing a GaAsP diode that emits red light. GaAsP can also be epitaxially grown on a GaP substrate. Or again, G
The aP can also be doped with isoelectronic impurities, such as nitrogen, in amounts sufficient to cause a spectral shift from green to yellow or yellow-green. In either case, the underlying GaP crystal is transparent to light emission. Other combinations and materials will be readily envisioned by those skilled in the art to provide different color or multicolor displays. From the foregoing, it will be understood that the several objects of the present invention are achieved and other advantages are obtained as well.The embodiments shown are for illustration only and without departing from the scope of the invention. It will be obvious that various modifications may be made to the structure and arrangement.

Accordingly, everything contained in this description or shown in the accompanying drawings should be interpreted as illustrative only rather than limiting.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a typical display array in the form of an X-Y matrix of integrated circuit memory devices and light emitting devices according to the present invention. FIG. 2 is a simple schematic diagram of one row in an X-Y matrix illustrating the operation of a memory element in combination with a light emitting device. FIG. 3 is a detailed 2×2 schematic diagram of a memory element and a light emitting device. FIG. 4 is a cross-sectional view of an integrated semiconductor light emitting display array according to the present invention. and,
FIG. 5 is an enlarged cross-sectional view of one of the so-called crystal mesas in which such a light emitting device is formed. Corresponding reference characters indicate the same parts throughout the drawings. 10...
・Composite integrated circuit light emitting display array, 11...X counter, 12...Y counter, 16...
・AND gate, 2011~20ni... Light emitting p-n coupled diode, 2111~21ni...
・Memory circuit element (flip-flop), 31, 32・
...Multi-emitter transistor, 33, 34.
...Resistor, 35...Transistor, 3
6, 37, 38...Load resistor, 39...
...Drive transistor, 40...Load resistor,
41... Light emitting diode, 43... Monolithic array, 44... Monolithic
silicon integrated circuit, 45...interconnect, 47
... pn junction region, 48 ... grid, 50 ... mesa.

Claims (1)

[Claims] 1 A composite integrated circuit light emitting display array, each of which has an LED
each LED device is comprised of a transparent monolithic GaP crystal, and each LED device is configured to emit light that is visible from the front of the array when energized; a monolithic array consisting of at least one diode with a light-emitting p-n junction provided on the back side of the LED device, selected to correspond to and to energize each of said LED devices; a monolithic integrated circuit array of physically addressable memory circuit elements; a backside sandwiched interconnection device, said circuit element selectively energizing said light emitting device when addressed to emit light visible from the front side of said crystal array; The above-described multiple integrated circuit light-emitting display array, characterized in that the above-described interconnection device is operable to extend the display.