JPS5916441B2 - demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a demodulator in which the DC level of the demodulated output is stable.

FIG. 1 shows a schematic diagram of a phase-shift synergistic demodulator of a conventional IC.

The inside of the IC is inside the broken line. First, to explain the operation of the IC circuit, a signal is inputted from input 1, is amplified by differential amplifier 2, and its output is amplitude limited and becomes a square wave.

This square wave is connected to the first
The signal is inputted to a switching circuit 1, whose phase is shifted by approximately 90° via a simultaneous phase shifter 3, and then inputted to a second switching circuit I formed of transistors 8 and 9.

The combined current of the first switching circuit input and the second switching circuit input flows through the load resistors 5 and 71 of the transistors 8 and 9, and is converted into a voltage.

This voltage conversion component increases in proportion to the phase difference 1 between the input signals of the first and second switch circuits, increases at the output of the transistor 8, and decreases at the output of the transistor 9. Applied to the base of 15°16.

This base voltage difference (thus transistor 15.16
This causes a difference in collector current l.

The current flowing through the transistors 15 and 161 is designated as 11 and 12, and the current flowing through the external resistor 20 of the IC is 11 and 12, and this is the switching input to the first switching circuit and the second switching circuit. The phase difference between the signals is proportional to l.

Since this phase difference changes in proportion to the input frequency of the phase shift circuit 3, a voltage indicating the S-curve characteristic of the FM demodulator is obtained at the end of the resistor 20.

However, at the reference operating point where 11 and 12 are equal, the resistance 2
Since the voltage drop at the 0 end is zero, transistors 16 and 1
A DC bias is applied to the collector 7 via a resistor 20 and a reference voltage (hereinafter referred to as Vr) 21 from outside the IC.

If there is no input signal and there are no variations in the VBE, resistance, etc. of each transistor in the IC, 11 1. , -Q with■
.

-Vr-〇 (Vo is the output voltage appearing at the terminal 22), but in reality, this is impossible because there is no variation, so Vo
'Vr〆0 (this is called an offset voltage).

When this (Vo Vr) is used as the control voltage for AFC, the sensitivity of AFC will vary depending on the fluctuation of (Vo-Vr), and in extreme cases, when the AFC is turned ON, the tuning point will change. It comes off.

Hereinafter, the fact that an offset voltage is generated due to element variation E will be explained in detail in Q).

In principle, a switching circuit can only take two states, OFF and ON, but in this case, switching circuits using active elements such as transistors are shown in Figures 2 and 3.
As shown in FIG. 1, there is a variable resistance region in the middle of switching.

In FIG. 2, a represents the input versus output voltage characteristic of the switch circuit consisting of transistors 8.9, b represents the input versus collector current characteristic of the switch circuit consisting of transistors 15 and 16, and C represents the input versus collector current characteristic of the switch circuit consisting of transistors 8. Transistor 15.16t
This represents the characteristic of the difference current flowing through the output voltage versus the output voltage.

For example, when the Vbe voltage of transistor 8 is made higher than the Vbe voltage of transistor 9, the DC level of input waveform 27 changes from 26 to 29) as shown in Figure 2.
If only this Vbe difference Vi is removed, the collector output waveforms of transistors 8 and 9 become 281.282.

Therefore, the output current waveforms of the transistors 15 and 16 are 401 and 402 as shown in FIG. 2, and the output voltage waveform of the output terminal 22 is 41 as shown in FIG. Here, the DC level indicated by A and B (
(level when there is no signal) are A" and B" in FIG. 2C, and the offset voltage is Vo□.

However, if the input waveform is sufficiently large and is a square wave as shown in FIG.
Even if O is present, the output waveform 41 is the same as the waveform 41 when there is no input offset pressure, and the integrated voltage is also Vr.

However, in reality, because the frequency band of the preamplifier is narrow, a perfect square wave cannot be obtained as the switching input signal.
For example, in an FM receiver receiving a weak electric field, the input waveform of the demodulator is close to a trapezoidal wave (sine wave) f as shown in 30I in FIG. 3a.

Figure 3 a, b, and c are characteristic diagrams of a switching circuit consisting of transistors 8 and 9, respectively, and characteristic diagrams of a switching circuit consisting of transistors 15 and 16. FIG. 2 is a differential current vs. output voltage characteristic diagram.

Such trapezoidal wave human power [here, V b as mentioned above
When the differential voltage Vi exists, the collector output voltage waveform becomes 311 and 312 as shown in Fig. 3A, and the collector current waveform of the next stage becomes 432°4 as shown in Fig. 3B.
33, and the output voltage waveform obtained from the output terminal 221 becomes 44 as shown in FIG.

Therefore, this integrated voltage becomes V r −Vo 2,
An offset of Vo2 occurs in the output voltage l.

An object of the present invention is to provide a demodulator that does not generate the above offset voltage.

In the present invention, a DC negative feedback path is provided between the input and output of the demodulator,
This suppresses the occurrence of offset voltage.

The present invention will be explained below with reference to FIGS. 4 and 5.

FIG. 4 shows an embodiment of the present invention using a phase-shift synergistic demodulation circuit E and a negative feedback circuit.

In FIG. 4, the base bias of transistors 8 and 9 constituting the second switching circuit is resistor 37.38.
The FM signal from the input terminal 39 is also supplied to the base of the transistor 8.

The simultaneous input signals are passed through the phase shifter 3 from the base of the transistor 8, shifted in phase by approximately 90 degrees, and sent to the transistor 10.
and 11 is input to the first switching circuit.

In proportion to the phase difference t between the input signals between the first switching circuit and the second switching circuit, current flows through the resistors 5 and 7 connected to the collectors of the transistors 8 and 9 of the second switching circuit. flows.

This current performs a differential output operation such that an increased current flows through the resistor 51 and a decreased current flows through the resistor 7.

The output voltage converted by the resistors 5 and 7I in proportion to the phase difference is applied to the bases of the transistors 15 and 16.

A current flows through the collectors of transistors 15 and 16 in response to the change in base voltage.

If the currents flowing through the transistors 15 and 16I are 11 and 12, currents of 11 and 12 flow through the resistor 20f.

This is proportional to the phase difference between the switching signals input to the first switching circuit and the second switching circuit,
Since this phase difference changes in proportion to the input frequency I of the phase shift circuit 3, the output terminal 221 obtains a demodulated output voltage according to the S-curve characteristics of the FM demodulator, and the terminal 23 obtains this demodulated output voltage. A DC voltage obtained by smoothing the voltage through the capacitor 331, that is, a DC component excluding the alternating current component in the demodulated output voltage is obtained.

At the reference operating point where 11 and 12 are equal, the voltage drop across the resistor 20 is zero, so the collector voltages of the transistors 16 and 17 are equal to the voltage Vr of the power supply 21.

If there is no input signal and there is no variation between each element within the IC, V at 11-12-0.

Vr=0 (VO is the output voltage appearing at the terminal 22).

However, in reality, this is impossible because there is no variation, so Vo
Vr〆0.

Now, assume that the difference between the base voltages of transistors 8 and 9 constituting the second switching circuit is ΔVB%, and the gain of the second switching circuit with respect to ΔVBEC is G1.

G as the difference between the base voltages of transistors 15 and 16
1.ΔvB, and if the gain of transistor 16 is G2.

The voltages G1, G2, and ΔvB appear across the resistor 20 as offset voltages.

However, since the resistor 20 also serves as a feedback resistance from the output terminal 22 to the base terminal 23 of the transistor 9, negative feedback is applied from the output terminal 22 to the base of the transistor 9.

If the amount of feedback is β, then the offset voltage due to the difference l between ΔvB is expressed as: 01G2)■, β-1, the offset voltage is only Δ■3, which is very small.

In addition, if an incomplete square wave as shown in FIG. 3 is input to the input/output terminal 39 (see FIG. ) This generates an offset voltage, which is negatively fed back to the base of the transistor 9 via the resistor 20 to produce an offset voltage V.

Perform one operation so that -Vr=O. That is, resistance 2
0, from the DC negative feedback means t consisting of a capacitor 33,
The offset voltage that occurs when the first and second differential amplifiers operate as DC amplifiers due to incomplete switching is suppressed.

FIG. 5 shows the characteristics of the input pair (Vo Vr) when the feedback of the present invention is used and when it is not used in the first embodiment shown in FIG. 1.

The measurements were carried out by placing an intermediate frequency amplifier (voltage gain path 73aB) in front of the demodulator of the present invention.

The horizontal axis is the input level (OdB=1μ■), and the vertical axis is (Vo
Vr).

When no feedback is applied, (■o-vr) changes greatly depending on the input level l, and its value also changes from 1.4V to 0.5■.

However, when feedback is applied, the input level t remains almost constant,
The value is also very small, ranging from 50mV to 130mV.
This shows that the effect of repatriation is large.

Furthermore, the present invention generates the DC bias voltage for the output stage inside the IC, eliminates external components, achieves high integration, and reduces costs.

[Brief explanation of the drawing]

FIG. 1 shows a schematic diagram of a conventional FM signal demodulator IC using switching means. FIGS. 2 and 3 show diagrams of the operating principles of a switching circuit using active elements, depending on the input waveform l. FIG. 4 shows an embodiment of the invention. FIG. 5 shows measurement data showing the effects of the circuit of the embodiment shown in FIGS. 1 and 4. 8.9...Second switching circuit, 10.1
1...First switching circuit, 15, 16.
17... Differential amplifier transistor, 20...
...Resistor for negative feedback, 21 ... DC power supply for setting reference operating point, 22 ... Demodulation signal output terminal,
33... Capacitor, 39... FM signal input terminal.

Claims (1)

[Claims] 1 A first differential amplifier, a second differential amplifier connected to serve as a load for the first differential amplifier, and an FM signal input to one differential amplifier and an FM signal input to the other differential amplifier. A phase shift means for producing a phase shift of 90° at the center frequency between the input FM signal and the input FM signal from the output of the second differential amplifier.
A demodulator having a load means for taking out the demodulated output signal (in which the DC component of the output signal is negatively fed back to the input side of the second differential amplifier to eliminate fluctuations in the DC component of the output signal). A demodulator characterized in that it is provided with negative feedback means for suppressing direct current.