JPS5916455B2 - Start-up control method for electronic equipment - Google Patents

Description

[Detailed Description of the Invention] The present invention identifies whether a received signal is a regular signal or noise in a data transmission device, etc., and starts and controls the transmission device, etc. when the signal is a regular signal. This invention relates to a start-up control method for electronic devices.

For example, a start signal (
For example, in a data transmission device that starts up the data transmission device and collects data by sending a calling signal, a noise detection circuit is installed in the data transmission device to prevent false startup due to noise. When the noise is detected, it is necessary to prevent the data transmitting device from being activated by the noise.

Conventionally, a noise removal circuit using a signal wave circuit, for example, is installed in the front stage of the start signal receiving circuit, or a delay time is set in the start signal reception operation to prevent false start due to noise, but none of these methods work. Although it is effective against pulsed noise, it has the disadvantage that it cannot be an effective noise removing means for other noises, such as noise similar to a start signal.

In addition, especially in a method in which a delay time is provided for the reception operation of the startup signal, the startup time of the device is delayed by the above delay time from the arrival of the startup signal, so this method is not suitable for electronic devices that require particularly high-speed processing. It cannot be called a method. The purpose of the present invention is to eliminate such conventional drawbacks, prevent erroneous activation of data transmission equipment due to noise, and thereby prevent delays in processing operations in electronic equipment such as data transmission equipment. An object of the present invention is to provide a start-up control method for an electronic device.

J For this purpose, the present invention focuses on the fact that the duration of noise is generally shorter than the duration of the activation signal, and also takes advantage of the fact that data transmission devices usually use clock pulses for their control. The duration of the received signal is monitored by means of a clock pulse, and activation of the device begins as soon as said signal is received, and if said signal is determined to be noise from its duration, said device is activated. The startup of is now stopped (reset).

Embodiments of the present invention will be described below with reference to FIGS. 1 to 4.

Fig. 1 is a circuit configuration diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of what is indicated by symbol 4 in Fig. 1, Fig. 3 is a time chart showing the operation of Fig. 1, and Fig. 4 is a time chart showing the operation of FIG.

In FIG. 1, 1 is a signal input terminal, 2 is a clock pulse generator, 3 is a signal receiver, 4 is a pulse counter, 5 is a data processor, 6 and 8 are AND gates, 7 is an inverter, and 9 is an OR gate. , a to i are symbols added for convenience to explain the operation.

Also, in Fig. 3, A is a time chart showing the operation when a regular signal (starting signal) is input to input terminal 1, and B is a time chart showing the operation when noise is input to input terminal 1. a-1 shows the waveform at the location marked a-1 in FIG. In the pulse counting section 4 shown in FIG. 2, 41, 42 and 43 are first, second and third counters, respectively, and 44 is an AND gate.

The clock pulse generator 2 constantly sends out clock pulses of, for example, 400 Hz, and a regular activation signal has a duration corresponding to N clock pulses, for example, 20 msec if it corresponds to 8 clock pulses. is input to input terminal 1.

The signal receiving section 3 receives (
(Whether it is an activation signal or noise), the high level (hereinafter expressed as 〃H〃) is reached at point (b).

), and the AND gate 6 is kept open. As a result, a clock pulse is supplied to the pulse counter 4, and regardless of whether the signal is a starting signal or a noise, the processing operation within the device is controlled as will be explained later with reference to FIG. The supply of signals (various clock signals) to the data processing unit 5 is started. In addition, the signal receiving section 3
is output to point i through the OR gate 9 or is reset by a set pulse, and the level at point b returns from H to low level (hereinafter expressed as L). When the AND gate 6 opens, the pulse counting section 4 counts the clock pulses from the clock pulse generating section 2, and sends various clock signals necessary for controlling the data processing section 5 to the point g, and inputs them to the input terminal 1 at the point d. A pulse is sent to identify whether the signal received is an activation signal or noise.

Here, the operation of the pulse counting section 4 will be explained in advance using the circuit diagram shown in FIG. 2 and the time chart shown in FIG. 4. The first counter 41 is N-ary (for example, octal)
It is composed of a counter, and outputs a pulse to its 8C terminal every time it counts N clock pulses sent to point c (e.g. 8 clock pulses), thereby transmitting the length of 1 bit of data to point g. A determining clock signal is sent out (Fig. 4,
41 (8C)) and outputs a pulse to the 5C terminal every time M clock pulses (for example, 5, M<N) are counted during the counting of N clock pulses. A clock signal is sent out that specifies a point approximately in the middle of (see "41 (5C)" in FIG. 4).

Furthermore, a pulse is output to the 1C terminal at the first clock pulse count in each operation of counting N clock pulses, thereby sending a clock signal specifying the start time of 1 bit to point g. The second counter 42 is composed of a P-adic (for example, decimal) counter that counts P bit signals (for example, 12) bit signals (clock signals that determine the length of 1 bit) sent from the first counter 41. Part 1 every time
A pulse is output to the 2C terminal, thereby sending a clock signal to point g that determines the number of bits (for example, 12 bits) constituting one word of data (see "42 (12 bits)" in Figure 4).
In addition, at the count of the first bit signal in each operation of counting P bit signals, a pulse is output to the 1C terminal. A clock signal specifying the bit (bit) is sent (see "42(1C)" in FIG. 4).

The third counter 43 is composed of an R-base (for example, quinary-base) counter, and receives the word signal sent from the second counter 42 (a clock signal sent every time a word ends) by R times (
When counting (for example, 5 pieces), an output is sent to the 5C terminal, thereby sending a clock signal to point g to identify the end of one piece of data. Before a signal (pulse) is input to the first, second and third counters 41, 42 and 43, their 1C terminals are in the "H" state and all other output terminals are in the "L" state. Each time a signal (pulse) is input to the input terminal T, the "H" state moves to the adjacent terminal.

In other words, when the first signal (pulse) is input, the 1C terminal becomes
The 2C terminal changes from "H" to "L" and from "L" to "H", the other output terminals remain unchanged at "L", and the 2C terminal changes from "L" to "L" when the second signal (pulse) is input. changes from "H" to "L", the 3C terminal changes from "L" to "H", and the other output terminals remain unchanged at "L", and this operation occurs when the third and subsequent signals (pulse) is input. Also, via point i, the set terminal R
A reset pulse is input, and the output returns to its original state, that is, the 1C terminal is ``H'' and all other output terminals are ``L''. In the three counters operating as described above, the 5C terminal of the first counter 41, the 1C terminal of the second counter 42, and the third counter 43
AND gate 4 of the respective outputs of the 1C terminal of
4, only the pulse that is output to the 5C terminal of the first counter '41 in the middle of the first bit of the first word is sent to point d.

That is, as shown in FIG.
Both the C terminal and the 1C terminal of the third counter 43
H is present only when it corresponds to the first bit of the first word, and only at this time the AND gate 44 is opened and the output of the 5C terminal of the first counter 41 is transmitted to point d. After the data processing section 5 performs predetermined data processing based on the various clock signals from the pulse counting section 4 described above, it outputs a set pulse at point h and sets itself.

First, the operation when a start signal is input to the input terminal 1 will be explained with reference to A in FIG. 3.

When a starting signal is input to input terminal 1, point a changes from "L" to "H", and during the duration of the starting signal, for example, 20 m.
``H'' at point a is maintained for sec.

When the point a changes to "H", the signal receiving section 3 generates an output, and the point b changes from "L" to "H". This signal receiving section 3
The output continues until the set pulse is output at point i. The AND gate 6 is activated by the H output of the signal receiving section 3.
is opened, and the clock pulse sent from the clock pulse generating section 2 is outputted to point c through the AND gate 6, and this clock pulse is input to the pulse counting section 4.

The pulse counting section 4 counts the clock pulses sent through point c, and sends one pulse to point d when M pulses, for example 5 clock pulses, have been counted during the operation of counting the first bit of the first word as described above. Send out.

On the other hand, the change from "L" to "H" at point a is inverted by the inverter 7 and transmitted to point e, which changes from "H" to "H".
This corresponds to N clock pulses, for example, 8 clock pulses, which is set as the duration of the start signal while the start signal changes to "L" and the point a is kept at "H", that is, after the start signal is input to input terminal 1. time (clock pulse frequency 40
The above-mentioned point e is kept at "L" for a period of 20 msec (assuming 0 Hz), and the AND gate 8 remains closed during this period. In addition, as mentioned above, the pulse sent to point d is the Mth clock pulse for counting the first bit of the first word, for example, the 5th (corresponding to 9) (when the frequency of the clock pulse is 400 Hz, the clock pulse is started). 10 after the signal is input
However, at this time, the start signal is continuing and the AND gate 8 is closed, so the pulse output to the point d is not transmitted to the point f. Therefore, no set pulse is output to point i to reset the signal receiving section 3, and the signal receiving section 3 continues to operate, keeping the AND gate 6 open, and the clock pulse is not output from the clock pulse generating section 2. The clock signals are input to the pulse counting section 4, and the pulse counting section 4 sends out various clock signals to the data processing section 5 according to the operations described above, and the data processing section 5 performs predetermined data processing based on these various clock signals. will be carried out.

When the predetermined data processing is completed in the data processing section 5, a set pulse is output from the data processing section 5 at point h, and this set pulse is transmitted to point i through the OR gate 9.
The signal receiving section 3 and pulse counting section 4 are reset and the series of operations is completed.

Next, the operation when noise is input to the input terminal 1 will be explained with reference to B in FIG. When noise is input to the input terminal 1 and the point a changes from L to H, the signal receiving section 3 is activated, and when the point b becomes H, the AND gate 6 opens and the clock pulse generating section is activated at the point c. A clock signal from 2 is sent out.

As described above, this causes the processing operation to start within the device. The pulse counting section 4 counts the clock pulses sent to point c, and sends a pulse to point d when it has counted M clock pulses, for example, 5 clock pulses, as described above.

Assuming that the frequency of the clock pulse is 400Hz, the pulse output to the above point d is generated 10 m after the pulse counter 4 is activated, that is, after the noise is received by the signal receiver 3.
It will be output on the ridge.

The noise is usually very short in duration, around 10 msec.
The noise that continues during this period is almost non-existent.

Therefore, by the time the pulse is output to point d, the noise has already disappeared, and point a has become "L". Therefore, at this time, the point e is set to H by the inverter 7, and the AND gate 8 is open, so the pulse outputted to the point d passes through the AND gate 8 and reaches the point f. It is output as a reset pulse.

This reset pulse is input to the signal receiving section 3 and the pulse counting section 4 through the OR gate 9, and resets each of them, so that everything returns to the state before noise reception.

When noise is received in this way, the pulse counter 4 is reset after counting the first M clock pulses, for example, 5 clock pulses.
No data processing is performed.

As explained in detail above, the present invention uses clock pulses to monitor the duration of a signal, and detects as noise any signal whose duration is less than or equal to a predetermined number of clock pulses. It is possible to effectively detect noise of any nature and restore the data transmission device, and regardless of whether the received signal is a regular activation signal or noise. The system starts the processing operation in the data transmission device for the time being, continues the above processing operation when the signal is a start signal, and resets the above processing operation when there is noise. Therefore, the processing operations within the device will not be delayed, and since it uses clock pulses normally used in data transmission devices, it can be realized with an extremely simple circuit configuration.The method according to the present invention is an extremely rational noise identification method. It provides a startup control circuit that includes functions, and its effects are extremely large.

Note that in this embodiment, the duration of the activation signal (calling signal) was set equal to the length of 1 bit of data to be processed, but it is not necessary to do so, and it may be set to be longer than the expected duration of noise. Then, the present invention can be implemented.

In addition, the number of clock pulses to be outputted to point d to detect noise is determined as appropriate, taking into account the length of the activation signal (calling signal) and the expected length of the noise. This is a design matter.

Further, the present invention can be implemented in any device, not just a data transmission device, as long as a pulse generator is provided, and the device to be implemented does not limit the gist of the present invention.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a pulse counting section of the embodiment, Fig. 3 is a time chart of the embodiment, and Fig. 4 is a time chart of the pulse counting section of the embodiment. It's a chat. Main symbols: 1...Input terminal, 2...Clock pulse generator, 3...Signal receiver, 4...
. . . Pulse counting section, 5 . . . Data processing section, 41 to 43 . . . Counter.

Claims (1)

[Claims] 1. It has a signal receiving section that receives and starts a starting signal and generates a signal for processing operation within the device from the starting point of the starting signal, and a pulse generating section that outputs a clock pulse,
The duration of the starting signal is set to the time during which N clock pulses are output from the pulse generating section, and M clock pulses are output from the pulse generating section counting from the starting point of the starting signal received by the signal receiving section. A logical product is performed between the second clock pulse (where M<N) and the activation signal, and the logical product output selects whether to continue activation of the signal receiving section or to reset it. start-up control method for electronic devices.