JPS5917456B2 - Buffer memory write control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory write control method, and in particular, a parallel method for writing variable length encoded input signals that have information only in the length of the code to the buffer memory. The present invention relates to a buffer memory write control system that allows use of a low-speed clock signal and performs write processing with low power.

When writing data sent from the code generator to the buffer memory, if the data generation rate is f3 and the maximum length of the variable length code expressing the data is m bits, the data is written to the buffer memory. The maximum bit processing speed for sequential writing is mf3.

Considering a 4MTV signal as a signal source, f328MHz
When m=16, the maximum processing speed of the buffer memory is as high as 128MH2. For this reason, elements capable of high-speed processing, such as CML, have conventionally been used in parts that require high-speed processing. However, this element has the disadvantage that it consumes a lot of power, and the power consumption of the entire device inevitably becomes large. If the number of bits m becomes even larger, it becomes technically impossible. Conventionally, data is converted into a fixed-length code, stored in a buffer memory, and then converted into the original variable-length code after being output from the buffer memory. The drawback was that the memory capacity had to be larger than necessary.

In order to eliminate these drawbacks, the present invention sets each code length to M0d.
The purpose is to integrate by 2n and write logic "10" only in the position corresponding to the integrator output value, so that a low-speed clock can be used and writing can be performed with low power.

The drawings will be explained in detail below. The figure shows the configuration of an embodiment of the present invention, in which reference numeral 1 is an input terminal, 2 is an n-bit adder, 3 is a D/D converter, 4 is a hold circuit, 5 is a delay circuit, and 6 is a flip-flop. , 7 is a buffer memory.

The signal input from input terminal 1 is an n-bit binary code. For example, if the input signal is "0011", the value "3" indicates that the code length of the variable length code is "3". . The output of the n-bit adder 2 represents the integral value of the code length of the variable length code. When the output of the n-bit adder 2 is N, the D/D converter 3 converts it into D/D and outputs 7'1'' to only the Nth bit from the bottom and ``O'' to the other bits. .For example, if the above output N is "0101", then 2
As an n-bit signal [00000000000100
00] is output. The hold circuit 4 is composed of a flip-flop 6 and a delay circuit (including zero delay time) 5, and sequentially stores the signal "1" sent from the D/D converter 3, and the n-bit adder 2 overflows. Hold until. That is, for example, until the n-bit adder 2 overflows, the signal "000000000000010
0" and [0000000010000000], the hold circuit 4 stores "000000001.
0000100" is stored. Buffer memory 7 simultaneously stores the contents of hold circuit 4, that is, the contents of data signal 2n bits, using the overflow signal of n-bit adder 2 as a clock. In order to make the explanation easier to understand, an example will be given.

Now suppose that a variable-length coded human signal with information only in the code length is sequentially "0010", [0011], "101".
It is assumed that ``0'' and ``0011'' are input. (1)
In this case, when the human input signal "0010" is input manually, the n-bit adder 2 outputs "0010".

Converter 3 outputs the signal “0000000000000010”
is output, and the flip-flop 6 in the hold circuit 4 holds "j-0000000000000010". (2) Next, when the input signal "0011" is input manually, the n-bit adder 2 outputs "-0101".

This causes the converter 3 to output the signal “000000000001
0000'' is output, and the flip-flop 6 in the hold circuit 4 holds ``0000000000010010''. (3) Next, when the human input signal [1010] is input manually, the n-bit adder 2 outputs [1111].

This causes the converter 3 to output the signal “010000000000
"0000" is output, and "0100000000010010" is held in the flip-flop 6 in the hold circuit 4. (4) Next input signal “0011”
is added manually, the addition result of n-bit adder 2 is [10
010'', and the n-bit adder 2 overflows 0F.
At the same time, "0010" is output to the converter 3 side. Due to the above overflow, the contents of the flip-flop 6 in the hold circuit 4 are 1010000000001001.
0'' is stored in the buffer memory 7 as information in 16-bit units. Converter 3 then outputs the signal “000000
0000000010" is output, and a new "000000000" is output to the flip-flop 6 in the hold circuit 4.
0000010" is read. As described above, codes of different lengths are arranged in the buffer memory 7 in an irregular manner.

These codes are read out at a constant speed in the order in which they were entered into the buffer memory 7, and transmitted to the receiving side via a transmitter. The data series that reaches the receiving side undergoes the above processing (1)
Using the example mentioned above in ~(4), “00100100
000000010010]. Note that this series is the content of the buffer memory 7 [0100
000000010010" are received sequentially from right to left,
Next buffer memory 7 contents “0000000000
It can be considered that this corresponds to the state in which up to 4 bits from the right of "000010" are received. Since the words in the above data series are separated by "1", count the number of bits from the first bit of "0" until the next "1" arrives, and use the count output as the decoded output. In other words, if you count the above data series from the right, there is 11/'' at the 2nd bit, so the counter is 2.
It counts up by bits and outputs the code "0010".

Next, the counter is first set. Then, the next "I" is counted from the next manually input "0" force), and since it is the third bit, the counter counts up by three bits and outputs the code [0011]. The counter repeats the same operation thereafter. As a result, the output of the counter is the same word sequence "0010j, [0011"] as on the transmitting side.
1010], "0011" is played. As explained above, according to the present invention, in order to store codes of different lengths side by side in the buffer memory 7, without performing parallel-to-linear conversion and serial-to-parallel conversion as in the conventional system. This is done through parallel processing using D/D conversion.

Therefore, there are advantages that the processing speed is not high, therefore high-speed elements are not required, the power consumption is low, and the buffer memory capacity can be reduced only by the effective amount.

[Brief explanation of drawings]

The figure shows the configuration of an embodiment of the present invention.

Claims (1)

[Claims] 1. A buffer memory having a buffer memory for sequentially storing variable length coded input signals having information only in the code length.
The memory control device is provided with an n-bit adder that sequentially adds the code lengths of the respective input signals, and the addition result of the n-bit adder is added until the addition result of the n-bit adder indicates a predetermined value. 1. A buffer memory write control method, characterized in that the data is held and sequentially stored in the buffer memory as the held predetermined units of information. 2. A digital-to-digital converter that converts the addition result of the n-bit adder into a 2^n-bit signal that converts the sign of the addition result to give information to the bit position corresponding to the addition result, and a predetermined output of the digital-to-digital converter. Claims characterized in that a hold circuit is provided to hold the data for a period of time, and the contents of the hold circuit are written into the buffer memory as information in units of 2^n bits in response to the n-bit adder carry signal. The buffer memory write control method described in item 1.