JPS5917468B2 - Program counter trajectory storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a program counter trajectory storage device, and more particularly to a program counter trajectory storage device for a computer controlled by a microprogram.

[Background of the Invention] In a conventional program counter trajectory storage device, as shown in FIG. , program counter 1
Data transfer from the storage device 3 to the storage device 3 is performed by microprogram control and the dedicated circuit 4, or by the dedicated circuit 4 alone! Among these methods, the method using microprogram control and the dedicated circuit 4 is used when the program counter output signal line 2 and the microprogram control signal line 5 are output from the computer main body 6 as standard. As shown in FIG. 2, after a multi-step microprogram T within an instruction is executed,
Further, a multi-step trace microprogram 8 is executed for each instruction, and the contents of the program counter 1 are thus transferred to the storage device 3.

Therefore, according to this method, the execution time of instructions increases by the amount of the trace microprogram, and especially when tracing is performed online, there is a significant delay in data processing, and correct debugging becomes difficult. There were flaws. On the other hand, if only a dedicated circuit is used, it does not affect the instruction execution time, but in addition to the output signal line 2 of the program counter 1, it is necessary to draw out a special signal line 9 for trace control. There was a drawback that many non-standard and special signal lines had to be drawn out of the computer main body 6 just for the trace function. [Object of the Invention] An object of the present invention is to eliminate the drawbacks of the above-mentioned prior art, and to output a large number of special signal lines to the outside especially for this purpose when tracing a program counter inside a computer. To provide a program counter locus storage device capable of tracing without having to use the program and without affecting instruction execution time at all.

[Summary of the invention]

In order to achieve the above object, according to the present invention, as shown in the block diagram of FIG. The common bus line 12 is output to the outside as a standard signal line, and the program counter to be traced is specified by the micro program address on the common bus line, and moreover, it is output once every instruction execution. is specified, and the contents of the program counter at that time are output to the memory address common bus line.Every time a program counter specified address on the micro program address common bus line 12 is detected, the contents of the memory address common bus line 11 are output. It is characterized in that the trajectory of the program counter is memorized by sequentially writing to a storage device 3 prepared separately.〇 [Embodiments of the Invention] The details of the present invention will be described below as examples. Explain using.

FIG. 4 is a diagram showing one embodiment of the program counter trajectory storage device according to the present invention, which traces the contents of a program counter indicating the address of a program instruction in order to trace an important program especially during debugging. In FIG. 4, which is an example of a case, the program counter locus storage device 21 is composed of, for example, one plug-in, and includes a data common bus 10 and a memory address common bus 1.
1. Microprogram address common bus line 12, memory drive signal line 20, and main memory output inhibition signal line 19
Both are connected to the computer main body as standard signal lines. The address common bus 11 has 16
A bit/1 kiloword shift register 3 is connected.
A detector 13 for detecting a microprogram address specifying a program counter is connected to the microprogram address common bus 12, and an output line of the detector 13 is connected to the shift register 3 through a delay circuit 16. The output line of the shift register 3 is connected to a temporary storage register 14, and the output of this register 14 is connected to a drive circuit 15 for outputting to the data common bus 10. The memory address common bus 11 is further connected to a memory address detector 17 used when reading out the contents of the storage device, and its output is connected to the data common bus drive circuit 15 through an AND gate 18 . Figures 5 and 6 show the operation time charts of a circuit with such a configuration.
As shown in the figure. However, FIG. 5 shows the case where the contents of the program counter are stored in the shift register 3, and FIG. 6 shows the case where the contents stored in the shift register 3 are read out. Generally, when a computer executes an instruction, the execution is divided into a step in which the instruction is fetched from the main memory (instruction fetch step) and a subsequent instruction execution step. At the instruction fetch stage, the contents of the program counter indicating the address of the main memory where the instruction is stored are output to the memory address common bus 11, but the address of the microprogram that executes this is limited to a specific one. Therefore, the address detector 13 connected to the microprogram address common bus 12 detects this address 22, and after a certain period of time this microprogram is executed, that is, the contents of the program counter 23 are detected.
When the memory address is output to the common bus 11, a signal 24 for writing and shifting the shift register 3 connected to the common bus 11 is output. Delay circuit 1
6 is for adjusting this time relationship, for example,
1 Delays the time required for microprogram execution 0
When a microprogram other than this microprogram is operating, the shift register 3 does not operate because the detector 13 does not detect it. When executing the next instruction, the contents of the program counter are stored in the next line of shift register 3 using the same operation. It will be done. In this way, in this case, the locus of the address of the instruction for one kilostep is stored. And beyond 1 kilostep,
Since it returns to the original state and stores the new contents of the program counter, the latest 1 kilostep trajectory is always stored.Next, when reading the contents of this shift register 3, A fixed address is determined in advance and the memory address detector 17 is set accordingly. When executing the instruction to read the set memory address, first, in the fetch stage, the address 27 of the previous instruction one kilostep is shifted to the temporary storage register 14, and then in the execution stage, the main memory address is shifted to the memory address common bus 11. When the memory drive signal 25 is detected by the memory address detector 17, the AND gate 18 is opened, the 1 drive circuit 15 is opened, and the contents of the temporary storage register 14 are output to the data common bus 10 and read out. be done. At this time, a signal 26 is output to the main memory output prohibition signal line 19 so that the contents of the same memory address in the main memory are not read out. If you continue this operation for 1 kilometer, you will know the trajectory of the command in 1 kilometer steps. As described above, according to this embodiment, the program counter can be traced without affecting the system at all by simply inserting one plug-in into the standard input/output device slot of the computer main body.

Reading the trace contents can be done in exactly the same way as reading the contents of main memory in a data typewriter. In other words, the contents of one specific memory address are sequentially stored 10 times.
It is sufficient to read it 00 times. [Effects of the Invention] As is clear from the above description, according to the present invention, there is no need to draw out any lines other than those outputted from the computer main body as standard signal lines, and there is no effect on the processing time of instructions. This makes it possible to trace the contents of the program counter without having to do so.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional program counter trajectory storage device, FIG. 2 is an explanatory diagram of the operation of the device shown in FIG. FIG. 4 is a diagram showing an embodiment of the program counter trajectory storage device according to the present invention, and FIGS. 5 and 6 are time chart trajectory storage devices for explaining the operation of the device shown in FIG. 4. 3...Storage device, 10...Data common bus, 11...Memory address common bus, 12
...Microprogram address common bus line, 1
3...Microprogram address detector, 2
1...Program counter trajectory storage device.

Claims (1)

[Claims] 1. In a program counter trajectory storage device of a computer in which a program counter is specified by a microprogram address on a common microprogram address bus and the contents of the program counter are output to a memory address common bus, the program on the microprogram address common bus A microprogram address detector for detecting a counter-specified address and a storage device for sequentially storing the contents on the memory address common bus each time the microprogram address detector detects a program counter-specified address are provided. A program counter trajectory device characterized in that the contents of a program counter are stored for tracing purposes.