JPS5917585B2 - solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a photodiode serving as a light receiving section of a solid-state imaging device and a switching MOS transistor connected thereto.

FIG. 1 shows an example of the configuration of a solid-state imaging device.

1 is one pixel of a light receiving section consisting of a photodiode 101 and a vertical switching MOS transistor 102.

2 and 3 are vertical and horizontal shift registers, respectively, and 1
03 is a horizontal switching MOS transistor, 104 is a video voltage source, 4 is a vertical gate line, 5 is a horizontal signal line, 6
is the signal output line.

FIG. 2 shows the cross-sectional structure θ of one picture element according to an embodiment of the present invention. T, 8 responds to 4, 5 in FIG. 9 is, for example, a P-type Si substrate (usually impurity concentration 10" CTr
(about L-3), 10 is polycrystalline Si for gate electrode, 11 is field oxide film, 12 is gate insulating film, 121, 12
2 is an N+ diffusion layer (impurity concentration 51020C7TL-3
13 is a p+ layer (usually impurity concentration 2 x 1015 (V71-3 to 101
Approximately 7cwL-3, formed by ion implantation, thermal diffusion, etc.)
It is.

13 is provided to cover the region of the diffusion layer 122. The advantages of providing the p+■0 layer 13 are listed below. Only the charge accumulated in the photodiode consisting of 1121 and 9 is taken into 122 through the gate of 10,
Charges photogenerated in other regions (due to the blooming phenomenon) can be prevented from entering 122 by using the barrier of the p+ layer 13.

The 2p+ layer 13 can prevent charges generated by light and charges overflowing from 121 from entering the horizontal signal line 8 through the drain region 122 30 deep within the substrate.

In other words, blooming can be suppressed by the p+ layer 13. FIG. 3 shows another embodiment.

14 is a p+ layer provided in the present invention, which is expected to have the same effect as shown in FIG. I can do things.

At the same time, this threshold voltage can be made higher than the threshold voltage of the peripheral circuit, and the tail current of the vertical switch MOS can be reduced.

FIG. 4 shows a p+ layer 16 added to FIG. 3, and 1
5 is the same p+ layer as 14. At the same time as p+ layer 15, p+
By forming the layer 16 by ion implantation, thermal diffusion, etc., the amount of junctions of the photodiode can be increased, and the amount of stored charge can be increased. Also, the p+ layer 16 is the N+ diffusion layer 12 of the photodiode.
Formed on part or all of the periphery of 1, p+ in the center
The layers are removed. This can prevent a decrease in sensitivity to long wavelength light due to the p+ layer. Furthermore, by forming a p+ layer around the periphery, excess charge due to blooming flows out from the region in the center of the photodiode where there is no p+ layer toward the substrate, so that a blooming suppressing effect can be expected. 17 in Figure 5,
Reference numeral 18 shows the impurity concentration of 15 and 16 in FIG. 4 changed.

17 is determined from the threshold voltage value, and the impurity concentration is 2×101
5-1016? -3, but 18 is determined from the junction capacitance, and the impurity concentration is about 1016 to 1017 CTrL-3.

19 and 20 in FIG. 6 replace the p+ layer 18 in FIG. 5 with the N+ layer 12.
1, which makes the pluming suppressing effect even more effective.

33 is the same as 17 in FIG.

In each of the above embodiments, an N-channel type device is used as an example, but it goes without saying that the present invention can be applied to a P-channel type device by reversing the conductivity types of the substrate and each impurity layer.

As described above, according to the present invention, not only is blooming suppressed, but also the storage capacity of the photodiode can be increased and the S/N ratio can be improved.

Furthermore, there is no reduction in resolution due to long wavelength light, and line exposure can be prevented. Furthermore, it can also be manufactured by a self-alignment method.
It is also possible to increase the threshold voltage of the transistor to FhI.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of the solid-state imaging device, Figures 2, 3, and 4.
5 and 6 are diagrams showing embodiments of the present invention. 9... P-type Si substrate, 10... Gate electrode, 11... Insulating film, 12... Gate insulating film, 13... p+ type layer, 121, 122
...N+ type layer (source, drain region).

Claims (1)

[Claims] 1 A semiconductor substrate of a first conductivity type, a source and drain region of a second conductivity type formed apart from each other on the surface region of the substrate, and a semiconductor substrate provided on the substrate surface between the source and drain regions with an insulating film interposed therebetween. In a solid-state imaging device having a gate electrode and using a source junction as a photodiode,
A solid-state imaging device characterized in that a first conductivity type region having an impurity concentration higher than that of the substrate surrounds the drain region and extends to at least a portion under the gate electrode.