JPS5918787B2 - TLB partition method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for time-sharing processing of a plurality of logical address systems using a TLB in a computer that multi-processes a plurality of programs, and particularly relates to an address conversion method in emulation mode.

When a computer system with multi-processing functions executes a program at the machine language level on another computer system with a different architecture under the management of an operating system, that is, when executing emulation, the computer system to be emulated. The address conversion from the logical address of the computer system to the real address of the computer system executing emulation is performed by software by referring to a conversion table in the main memory. FIGS. 1a and 1b show the relationship between an operating system and software that enables emulation when emulation is performed between computer systems.

In the figure, computer systems A and B have operating systems OSA and OSB that manage them, respectively, and each operating system OSA (50SB
The relationship is that when computer B emulates computer A's program, computer B's hardware emulation mechanism and the supporting software, the compatible executor OSA,
- Emulation is possible using EX.
Compatible executor OSA-EX executes the job program and operating system OSA of computer system A by virtually creating the hardware of computer system A on the hardware of computer system B. This compatible executor OSA-EX is under the control of the operating system OSB, and can be processed in parallel with other job programs by the operating system OSB. Here, when both computers employ a virtual memory system, the means for address conversion between the virtual addresses AL and BL and the real addresses AR and BR is as follows, assuming that the emulation is performed.
Figure 1c shows this relationship. That is, when computer system B emulates the program of computer system A, it is necessary to convert the logical address AL of computer system A into the real address BR of computer system B, and the Logical address AL created in advance under management
First, AR is obtained from the given AL using the real address AR conversion table TA, and then this real address AR is treated as the logical address BL of computer system B, and this is used in the operating system of computer system B.
Conversion table T between logical address BL and real address BR created in advance under the management of system 0SB
The real address BR corresponding to the logical address BL by B
is obtained. By the way, in order to convert a logical address to a real address, it is necessary to read the table entry 1 for address conversion twice, and the time required for this is all added to the overhead, so address conversion is an efficient method. Buffer memory TLB (Tra
nslatiOnLOOkasideBuffer).

However, since there is no way to refer to this TLB when different logical address systems are used, as in the case of emulation, the address is converted each time by software, which results in large overhead and inefficiency. Ta. SUMMARY OF THE INVENTION An object of the present invention is to provide an efficient address translation method that reduces overhead even if there are a plurality of different logical address systems under an operating system that performs multiple program processing.

According to the present invention, in an address translation mechanism using a TLB that obtains a real address output from a logical address input, the TLB
Within the address bits that specify the address, there are specific bits that are used redundantly in the address bits of the virtual address that is compared with the TLB entry, and the bits that identify different logical address systems depending on the combination of the specific bits. When a selection signal indicating that the logical address input is of a different logical address system is received, the TLB address is specified using the selection signal instead of the specific pit output when specifying the TLB address. , a TLB partitioning method is obtained in which the TLB is divided and used.

The present invention will be explained below with reference to the drawings.

FIG. 2 is a diagram showing the process of processing a job program in emulation mode. Here, the native mode is a mode in which the computer processes its own machine language, and the emulation mode is a mode in which the computer processes the machine language of another computer system. In the figure, JOB #1 and #2 are currently running natively under the direct management of operating system B.
At the same time, JOB #3 is operating in emulation mode under the management of compatible executor 0SA-EX. This emulation process is performed using DIL (DOInterpretiveLO
The Op) instruction tells that the processing program that follows is to be processed in emulation mode.

Also, this instruction is an instruction for executing a loop of the emulation program until there is an interrupt from another source or an unprocessable instruction. When there is no need to execute emulation using this DIL instruction, the native
mode and returns to the mode in which the computer processes its own machine language program. FIG. 3 is a block diagram of an address conversion system showing one embodiment of the present invention.

In this example, the logical address has an address bit length of 24 bits, and the address space is divided into two stages using the paging method: logical address 1 is divided into segment number 5 bits (0th bit to 4th bit) and page number 8. The logical address part L1 consists of 3 bits (5th bit to 12th bit) and the byte address Dll bit (13th bit)
bit to 23rd bit). Next, the real address 3 has an address bit length of 22 bits, and the real page address Rll bits (0th bit to 1st bit).
0 bit) and byte address Dll bit (11th
bit to 21st bit). In the figure, there are 256 entries in TLB2, in which a virtual address 7 and a real page address 8 are stored as a pair. Regarding normal address conversion using TLB2, when logical address 1 is given, the TLB address is calculated from the logical address.
The B address is selected by the decoder 4, and the comparison circuit 5 checks the virtual address part 7 of the TLB entry and the upper 6 bits of the logical address 1 to determine whether the desired real address is stored in the corresponding entry. are compared and determined. If a match is confirmed here, the real page address 8 stored in TLB2 and the byte address D of logical address 1 are added to form the real page address R and byte address D.
A real address 3 consisting of address D is created and address conversion is completed. If the above comparison results do not match, address translation for the corresponding logical address 1 to real address 3 is performed by referring to the address translation table in the main memory. Then, the real address corresponding to the newly obtained logical address is registered in the TLB2 via the signal line L3 for later address translation.

As an example, a case will be shown in which there are two types of logical addresses and each uses half of the TLB.

Type 1 with each logical address as type 1 and 2
Alternatively, if only type 2 exists, the lower 8 bits of the 3 bits of the logical address part that make up the segment and page number of logical address 1 are used for TLB address specification, and the remaining 5 bits are used for TLB address. TL is a combination of 1 bit (total 6 bits)
The real page address 8 corresponding to the virtual address 7 is indexed by comparing it with the virtual address part 7 of the B entry 1. This redundant bit section 9 that is used redundantly, that is, T
The positions of the bits shared by the LB address and the virtual address comparison are the same between type 1 and type 2. The position occupied by this duplicate bit part 9 in the logical address is type 1.
For example, by fixing SO'' to type 2 and S1, for example, it becomes possible to use half of the TLB. In other words, the emulation type shown in FIG.
The flip-flopgo is set by the selection signal L1 by the DIL command issued during the mode, and the flip-flopgo is reset by the selection signal L2 by the end of the DIL command, so that the output of the duplicate bit section 9 is set. By leaving the functions for virtual addresses as they are and replacing the output for TLB address specification with flip/flopgo output, it is possible to do so without restricting virtual address specification.
The TLB address can be divided and used depending on the emulation mode and native mode. By providing duplicate bit 9 as described above, bits 5 to 12 of logical address 1 can be used in native mode (generally only one logical address system needs to be used).
By using the TLB address as is to specify the TLB address, all 256 TLB entries can be used for one logical address system.

In addition, in emulation mode (generally when two or more logical address systems are frequently switched and used), TLB
A logical address system designation signal (flip/flopgo output) is used for the duplicate bit part for address specification, and the logical address 1 is used only as the duplicate bit part for virtual address comparison.
By using bit 5 of , the 256 TLB entries can be divided into two partitions each having 128 entries.

In either mode, the virtual address comparison operation when referencing the TLB and the virtual address writing operation when newly registering to the TLB can be made completely the same, and the circuit configuration and control are simple. In this way, the TLB can be divided and used, so even if there are three or more logical address types, the flip
If the number of bits of the flop is increased and selected and set by the DIL instruction according to the type of logical address, the TLB
The divided use of is further expanded.

As is clear from the above examples, emulation
By selectively setting some bits of the TLB address from the outside in multiple program processing in mode and native mode, multiple logical address systems can be used for address translation by dividing the TLB.
By reducing the overhead caused by address conversion in the mode, efficient program processing becomes possible.

[Brief explanation of drawings]

Figures 1A and 1B are explanatory diagrams showing the relationship between the operating system and the software that enables emulation when emulation is implemented, and Figure 1C is the concept of address translation by software between computers A and B. 2 is a diagram showing the processing process of a job program in the emulation mode, and FIG. 3 is a block diagram of an address conversion system showing one embodiment of the present invention. 1...Logical address, 2...TLBl
3...Real address, 4...Decoder,
5...Comparison circuit, 7...Virtual address section, 8...Real page address section, 9...
. . . Duplicate bit section, V . . . Flip-flop, Ll, L2 . . . Selection signal.

Claims (1)

[Claims] 1 TLB that gets real address output from logical address input
In the address translation mechanism using When a selection signal indicating that the logical address input is a different logical address system is received, the selection signal is made to correspond to a bit identifying a different logical address system when specifying the TLB address instead of the specific bit output. A TLB partitioning method characterized in that the TLB is divided and used by specifying the TLB address using a signal.