JPS5918793B2 - Semiconductor nonvolatile memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rewritable nonvolatile semiconductor memory device.

BACKGROUND ART As the amount of information handled increases, electronic devices that process this information are required to have large capacity and high speed operation, and the demands on storage devices in particular are becoming significantly stronger.

For this reason, the magnetic core matrix conventionally used as random access memory (RAM) is rapidly changing to semiconductor I/O.
It has been replaced by C memory. Although I am calm,
Conventional RAM, both dynamic and static types, has the disadvantage that the stored information disappears when the power is turned off, and if information non-volatility is required, it still requires low-speed operation. have no choice but to rely on magnetic memory. On the other hand, read-only memory (ROM)
Although programmable ROMs using mask patterning and phases are used in ROMs, there are many demands to rewrite electrically written information, which is not possible with these ROMs. In the past, there have been several prototypes of memory devices that allow this type of information to be rewritten and that the written information does not disappear when the power is turned off, but as an IC capable of large capacity and high speed operation, The most promising one is based on a metal-insulator-semiconductor (MIS) structure.

The basic principle of this is that electrons or holes are injected from the substrate semiconductor into a potential well formed in an insulating film to charge it, and the electrostatic force changes the semiconductor surface potential. It is something. The potential well formation method involves adding a thin layer of SiO2 to the Si surface.
Grow a film and deposit Al2O3 or Si3N4 on top of it.
There are methods that utilize interface traps created by stacking different types of insulating films, such as, and methods that bury metal or polycrystalline silicon in the insulating film and use this as a well. The charge injection method involves applying a pulse bias between the source or substrate and gate of the MIS type FET, and by tunneling, the carrier passes through thin SiO2 and reaches the potential well, and the source or drain. There is a method in which the Pn junction formed between the semiconductor device and the substrate is reverse biased, and hot electrons or holes generated by avalanche multiplication are injected into the potential well.

The operation speed of the former is faster due to the tunnel effect.
However, in order to increase the operating speed, it is necessary to make the SiO film thinner, which poses the problem of sharply decreasing memory retention. Furthermore, in devices with this conventional structure, carrier injection is performed from the semiconductor surface, and after repeated injection and discharge, that is, memory writing and erasing, many times, the SiO, -Si interface structure is significantly damaged. , a problem has arisen in which the electrical characteristics of the memory element deteriorate.

For example, in a conventional report, deterioration occurs after 103 to 104 rewrites, and such an element cannot be used as a RAM that undergoes electrical rewriting many times.

MIS type nonvolatile memory, which is based on the principle of not injecting or releasing potential wells in an insulating film from a semiconductor substrate, uses a ferroelectric material instead of an insulating film, and its dipole polarization Therefore, there are attempts to change the semiconductor surface potential. Si4T as a ferroelectric material
iO, O, 2, etc. are attached to the Si surface by high frequency sputtering and polycrystallized by heat treatment. In such memory devices, when operating at room temperature, which is well below the ferroelectric temperature, changes in orientation, that is, loss of memory, seem to be negligible.However, the biggest problem is that both ferroelectrics and semiconductors Although it is desirable to have single crystals, their hexeroepitaxy has not yet been found. Furthermore, there is a problem that the interface characteristics of the semiconductor deteriorate at the interface between the ferroelectric material and the semiconductor. The present invention provides an MIS type non-volatile memory device which has characteristics that significantly improve deterioration after repeated use, which is observed in any of the structures described above, by utilizing an information storage phenomenon based on a completely new structure. It is something.

The semiconductor nonvolatile memory device of the present invention includes, on the surface of a semiconductor substrate, a first insulating film each having a thickness of 10 to 100λ, a second insulating film on the first insulating film, and a second insulating film on the surface of the semiconductor substrate. a third insulating film located above and thicker than the first and second insulating films, and a gate electrode on the third insulating film, and a first insulating film between the substrate and the gate electrode; By applying voltage,
Charge is moved from the boundary between the first and second insulating films to the boundary between the second and third insulating films, and by applying a second voltage between the substrate and the gate electrode, the second
and a charge is moved from the boundary of the third insulating film to the boundary of the first and second insulating films, and the charge is moved to the boundary of the first and second insulating films or the boundary of the second and third insulating films. The device is characterized in that binary information is stored by accumulating charges, and this will be explained in detail below with reference to the drawings.

The basic structure of the semiconductor non-volatile memory device of the present invention is as shown in FIG. Then, an electrode material 5 such as a metal or a semiconductor is deposited to form an electron or hole trap having an electrically deep energy level at the interface between the insulating films 2 and 3 and the insulating films 3 and 4, respectively. It consists of things.

As a method for forming this trap level, the insulating films 2 and 3 or the insulating films 3 and 4 may be formed from different materials or by different production methods to make use of atomic dangling bonds, or at their interfaces. It is also possible to use a metal or the like that forms a deep energy level. In the latter case, the insulating film 2
and 3, or the insulating films 3 and 4 do not need to be different materials. In order to explain the operating principle of a memory element having such a structure, a potential energy distribution is shown in FIG. The potential for electrons is represented by the curve A. In FIG. 1, 6, 7, and 8 are high energy positions, and correspond to the positions of the insulating films 4, 3, and 2, respectively. Further, 9 and 10 are energy valleys, which correspond to the positions of the interfaces between the insulating films 3 and 4 and the insulating films 2 and 3, respectively. For example, applying a high positive voltage to the semiconductor substrate 1 (
When the voltage is applied to the (gate) electrode 5, the potential becomes lower in the order of 8, 7, and 6, and the electron 11 in the valley 10 of the first potential energy crosses the peak 7 of the potential and reaches the valley 9 of the potential. Thereafter, when the potential of the electrode 5 is made approximately equal to that of the substrate 1, the electrons 11 that have moved to the potential valley 9 are held at that position. On the contrary, when a negative voltage is applied to the electrode 3, the potential becomes lower in the order of 6, 7, and 8, and the electron 11 in the valley 9 of the potential moves to 10. The electrons 11 that have moved to the trough 10 of the intension are similarly held even after the applied voltage is removed. It is well known that the semiconductor surface potential varies depending on the amount of charge existing near the surface, and its magnitude is inversely proportional to the distance from the semiconductor surface to the charge. That is, when electrons 11 are accumulated at the potential valley 9 position, the semiconductor surface potential becomes low, whereas when electrons 11 are accumulated at the valley position 10, the semiconductor surface potential becomes high. As described above, the mechanism of the memory device according to the present invention utilizes the transition of electrons between traps formed inside the insulating film, so that electrons can be repeatedly transferred from the semiconductor surface into the insulating film as seen in conventional non-volatile MIS memory. There is no deterioration of interfacial or memory properties due to carrier injection or release. Furthermore, the mechanism by which electrons transfer between traps is due to the tunnel effect when the distance between them is short, resulting in extremely fast switching. In order to transfer charges between two insulating film interfaces by the tunnel effect with a write or erase voltage of a practical magnitude, the thickness of the insulating film 3 in FIG. 1 must be 100λ.
It is necessary that the following is true.

The thickness of the insulating film 2 is also set to 10 to ensure that the charges captured in the traps have a sufficiently large effect on the semiconductor surface potential.
It shall be 0λ or less. In order to speed up writing and erasing, it is desirable to configure the structure so that charges can directly move between traps by the tunnel effect, and for this purpose, the thickness of the insulating film 3 should be 50 Å or less, especially 30 Å or less. is desirable.
Further, the thickness of the insulating films 2 and 3 needs to be 10λ or more in order to prevent the tunnel effect from easily occurring and erasing the memory. In the memory device of the present invention, it is necessary to configure it so that the charge can be held at the insulating film interface without moving between it and the semiconductor substrate in either writing or erasing. 10
Since charge transfer due to the tunnel effect is more likely to occur between the two substrates due to the influence of fixed charges and the like, and the potential peak between the potential valley 10 and the semiconductor substrate 1 is high, it is not necessary to make the insulating film 2 thicker than the insulating film 3. Next, examples of the present invention will be described.

FIG. 2 shows a nonvolatile MIS memory transistor having an information storage function constructed according to the present invention.

In FIG. 2, 12 is S! containing n-type or p-type impurities! The substrate 13 and 14 are impurity diffusion layers of a conductivity type opposite to that of the substrate 12, and correspond to the source and drain of a normal MIS type transistor. 15 is Si with a film thickness of approximately 1 μm
This film not only serves as a mask for selectively forming insulating films 16 and 17 in the next step, but also reduces stray capacitance of wiring.

The thickness of the insulating films 16 and 17 is 10 to 100λ.
The most desirable and most suitable configuration is one using a silicon nitride (Si3N4) film and a SiO2 film, respectively. That is, after thoroughly cleaning the area where the insulating film 16 is to be formed with a solution containing HF, the area is placed in pure nitrogen heated to 1200°C, and the area where the insulating film 16 is to be formed is cleaned for about 35 minutes in 5 minutes.
A Si, N4 film 16 with a film thickness of λ is grown. Next, the surface of the Si3N4 film 16 is oxidized by taking it out into the air or heating it in an atmosphere containing oxygen, and the SiO
, a film 17 is produced. Next, an insulating film is deposited, which is made of Si obtained at a temperature of 700°C by thermal decomposition of ethyl silicate.
An O2 film 18 can be used. In addition, in order to increase the trap density between the insulating films 17 and 18, it is possible to use many kinds of materials such as a Si3N4 film formed by a reaction between SiH4 and NH3. Next, an electrode material such as Al with contact windows for the source and drain opened is deposited by vacuum evaporation or the like to form the source 19, gate 20, and drain 21 electrodes. The memory element configured in this way is 3×1
Si doped with boron to a concentration of 015crrL-3
When using a substrate, +50V is applied between the gate 20 and the base 12.
When a voltage of -50 is applied to the gate 20, the gate threshold voltage at which a channel is formed between the source and drain is about 130, and on the other hand, when -50 is applied to the gate 20, it is +30.
Such large fluctuations in threshold voltage are not observed in elements with other structures, and there is an advantage that a large noise margin can be secured. Furthermore, the speed of shifting to each of the states described above was comparable to or higher than that of the conventional element, and further, the deterioration after repeated writing and erasing was extremely small. Memory can be rewritten quickly and with low voltage. It also has extremely good memory retention characteristics, and has great practical value as a nonvolatile memory. In this embodiment, Si is used for the semiconductor substrate, but the substrate is not limited to this, and Ge or a compound semiconductor may also be used.

Further, the insulating films may be of any type as long as they produce traps at their respective interfaces, and many combinations are possible.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the basic configuration of a semiconductor nonvolatile memory device according to the present invention, and FIG. 2 is a diagram showing a semiconductor nonvolatile memory device according to an embodiment of the present invention. In the drawings, 1 and 12 are semiconductor substrates, 2, 3, 4, 1
6, 17 and 18 are insulating films, 5 and 20 are gate electrodes, and A is a curve showing potential energy distribution.

Claims (1)

[Claims] 1 A film thickness of 10 to 100 Å is applied to the surface of the semiconductor substrate.
a first insulating film, a second insulating film on the first insulating film, and a third insulating film on the second insulating film and thicker than the first and second insulating films; a gate electrode on the third insulating film, and by applying a first voltage between the semiconductor substrate and the gate electrode, the first insulating film and the second
The electric charge is transferred from the interface with the insulating film to the interface between the second insulating film and the third insulating film, and a second voltage is applied between the semiconductor substrate and the gate electrode. The charge is transferred from the interface between the second insulating film and the third insulating film to the interface between the first insulating film and the second insulating film, and the charge is transferred to the interface between the first insulating film and the second insulating film. Alternatively, a semiconductor nonvolatile memory device, characterized in that binary information is stored by accumulating charge on either one of the interfaces between the second insulating film and the third insulating film.