JPS5918907B2 - Time adjustment device for different types of synchronous video signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video device that digitizes a composite video signal such as an NTSC or PAL television signal and performs various processing, and particularly relates to a device that performs time alignment of different types of synchronized video signals.

Recently, it has become widespread to digitize television signals and perform various processing on them. In other words, analog signals are converted into digital signals in format conversion, VTR time base collectors, and combining different types of synchronized video signals in multi-channel broadcasting (television signals from broadcasting stations all over the country are centrally collected and broadcast after program production). This is because if this is done after digitization, operations such as storage and conversion can be performed freely, and signal deterioration in the digital stage is considered to be purely due to the method. When performing these processes, it may be necessary to uniquely determine the position of each pixel with respect to a temporal reference position.

FIGS. 1 and 2 illustrate such a typical case. That is, in FIG. 1, 100 is an input terminal for a digitized video signal, 101 is a memory, 102 is an output terminal for signals successively output from the memory 101, and 105 is a write terminal for specifying an address when writing a signal into the memory 101. IOT is a read address counter that specifies the address when reading signals from the memory 101;
Terminal 103 is an input terminal for a signal to set the write address counter to a predetermined state, terminal 108 is an input terminal for a signal to set the read address counter to a predetermined state, and terminal 104 is a clock for the write address counter. An input terminal, terminal 109 is a clock input terminal of a read address counter, 106 is an address switching circuit, 110 is an address counter 105,
This is a terminal into which a signal is input to instruct the address switching circuit 106 as to which of the addresses designated by 107 should be given to the memory 101, and is used for the phase combining device for different types of synchronized video signals and for the time base of a VTR. - This is a configuration used when correcting the time axis of a video signal in a collector, etc. An uncorrected digital video signal is input to the terminal 100, and a set signal at the terminal 103 is input to the terminal 1.
The clock at 04 is generated from the color subcarrier and synchronization signal of the uncorrected video signal, the set signal at terminal 108, the clock at terminal 109 is generated from the reference color subcarrier and the synchronization signal, and the clock at terminal 102 is generated from the color subcarrier and synchronization signal of the uncorrected video signal. A digital video signal can be obtained. In this case, the temporal position of the uncorrected video signal of the pixel written to the nth address of the memory 101 with respect to the synchronization signal and the phase of the color subcarrier, and the reference synchronization signal of the pixel read from the nth address and the temporal position relative to the phase of the color subcarrier must be equal. FIG. 2 is a waveform diagram showing the situation during this time, in which 200 is an uncorrected video signal, 2
01 is a corrected video signal, and 202 is a memory.

In this case, the time reference position is specifically the address
This can be thought of as the time at which a signal appears at terminals 103, 108 that sets counters 105, 107 to a predetermined state. A horizontal or vertical synchronization signal can be considered as a signal that provides this reference time, but in the case of an NTSC signal, for example, the phase of the color subcarrier is inverted (shifted by 1800) every horizontal scanning period and frame period, and analog・As the sampling pulse for digital conversion (hereinafter referred to as A/D conversion), a frequency that is an odd multiple (usually 3 times) of the subcarrier is selected, also considering frequency interleaving, but the phase of this pulse Therefore, it is inconvenient to use the horizontal or vertical synchronization signal as it is as a time reference, since it similarly deviates by 180 degrees for each horizontal scanning period and frame period.

In consideration of these points, the present invention provides an apparatus that digitizes television signals and generates reference signals, control signals, etc. necessary for processing the signals.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows an embodiment of the invention.

1 and 2 are monostable multivibrators, 3, 5, and 8 are 4
circuit, 4, 6, 7 are flip-flops, 9 is a counter,
10 is a logic circuit, 11 is a NOR circuit, 12 is a color subcarrier input terminal, 13 is a vertical synchronization signal input terminal, 14 is a horizontal synchronization signal input terminal, and 15 is a clock input terminal.

FIG. 4 is an operational waveform diagram, and A, b, c, d, and e are waveforms when obtaining signals of the frame period.

a is a horizontal synchronization signal, and b is a vertical synchronization signal. however,
It is assumed that the vertical synchronizing signal is adjusted to have the same phase as the horizontal synchronizing signal every other field. c is the output of monostable multivibrator 1, and d is the output of monostable multivibrator 2. e is the output of the AND circuit 3, and is a signal generated once per frame. FIG. 4F, g, h, i, j, k, l, m, and n show waveform diagrams when the initial value of the counter 9 is determined from the color subcarrier and the signal of the frame period. f is the signal e or a signal generated therefrom, and is a signal illustrated by enlarging the time axis of the signal e, or a signal with a constant phase relationship with e (obtained by waveform shaping e, etc.). signal). G, n are color subcarriers, h is the output of flip-flop 4, i is the output of M4 circuit 5, j is the clock, k is the output of flip-flop 6, 1 is the output of flip-flop 7, m is AND The output of the circuit 8, f, is adjusted so as to have a phase relationship with the color subcarrier as shown in the figure. In this case, if g is the color subcarrier of the Nth frame, then n
is the color subcarrier of the N±1th frame. Therefore, M4
An output pulse like i appears in the circuit 5 every other frame, that is, once every two frames. Counter 9 counts clock j (which has a frequency three times that of the color subcarrier), has a period of 2 frames, and has a period of 2 frames.
It is returned to the initial state through the R circuit 11 by the AND circuit 8 and the carry output of the counter 9. If Fsc is the color subcarrier frequency and FH is the horizontal synchronization frequency, then Fsc=(4
55/2)FH, and there are 525×2 horizontal synchronization signals in two frames. That is, since there are 455x3 clocks j during two horizontal scanning periods, there are 455x3x525 = 71 clocks j within two frames.
Therefore, when the counter 9 counts 716625 clocks, a carry output is output. This is expressed in binary as ``1010111011110101
0001'', it can be configured with a 20-bit (stage) counter.

The output of the AND circuit 8 is a pulse whose width is equal to one period of the clock j, which appears once every two frames. Therefore, the initial value of the counter 9 is set every two frames. On the other hand, since the counter 9 has a period of two frames as described above, it outputs a carry output every time it counts two frames worth of clock j from the initial value. If O' is set as the initial value, a carry output will be obtained by decoding the binary code, and the initial value will be set to 220-716625.
=331951, i.e. ″10100010000101
If it is 01111゛2, if you decode when all the stages become "r", you will literally get a single output.

Since the synchronization at which the output of the M1 circuit 8 is obtained is equal to the synchronization at the counter 9, = once the counter 9 is initialized by the output of the AND circuit 8, the carry output of the counter 9 is and the output of the M1 circuit 8 are in phase. Therefore, AN
The output of the D circuit 8 and the carrier output of the counter 9 are in the same phase, and each state of the counter 9 corresponds to the image signal of two frames.
There is a one-to-one correspondence with each pixel. Therefore, it is possible to reset the write address counter and read address counter of the memory by performing appropriate logical operations on the output code of the counter 9, for example, by decoding a predetermined state of the counter 9. If the logic circuit 10 performs operations such as generating a signal or generating a timing signal when inserting characters or other images into a part of an image,
Necessary signals can be obtained at any position for each pixel. By providing such circuits on the writing side and the reading side, it is possible to make the positions of pixels written at the same location relative to the reference position corresponding to the uncorrected signal and the corrected signal to be the same. .

By the way, the capacity of the memory 101 in FIG. 1 may normally be one frame or one field.

Since the period of the counter 9 is 2 frames, the logic circuit 10
By decoding a specific state of the counter 9 by , it is possible to obtain a pulse corresponding to any point in time between the two frames. For example, if the memory has a capacity of one frame, the address counter 105 or 107
It is only necessary to count pixels for at least one frame, and the reset signal need only be generated in the logic circuit 10 not only every two frames, but also in between.
Therefore, even with such a memory capacity, no inconvenience occurs. FIG. 5 shows another embodiment in which the numbers on each block are the same as the similarly numbered blocks in FIG.

In this case, the difference is that the clock of the counter 9 is configured to count the color subcarrier itself, and the number of stages of the counter 9 is reduced. In this way, the counter 9 in FIG.
By using a configuration that counts the color subcarrier itself as a clock, in order to have a cycle of 2 frames, it is necessary to count 238
It can be configured to return to the original state (so that a single output is output) by counting 875 (-525×455) clocks.

238875 is 11110100101000110
Since it is 11"3, it becomes an 18-stage counter.

A method of setting the initial value to "0" and making the decoded output of this binary code a single output, the initial value is 218-23887
5=23269, i.e. 610110101011100
As in the case of Fig. 3, there is a method in which the decoding output when all stages become 11" is set to 101".Therefore, as in the case of Fig. 3, For this reason, the phase of the output of the M4 circuit 8 and the carry output of the counter 9 become equal. FIG. , g correspond to F, g, h, i, k, and l in Fig. 4, respectively, and the signal corresponding to j in Fig. 4 also serves as b in Fig. 6. Fig. 7 is shown in Fig. 5. A circuit is shown in which a signal having the same pulse width as the signal obtained by the circuit in FIG. 3 is desired to be obtained from a signal having a width of one color subcarrier cycle obtained from the circuit.

Since the video signal is sampled at a frequency of 3fsc, the frequency of the address counter clock is also 3fsc.
Therefore, in order to reset the address counter (set the initial value) in synchronization with the clock, the address counter reset signal (load signal) must be synchronized with the clock, and the pulse width must be equal to the period of the clock. It is desirable that it be equal to , and in such a case the circuit of FIG. 7 is effective. This is not necessary if the above reset is performed asynchronously. This circuit is connected to the decode output of logic circuit 10, since the width of the decode output of logic circuit 10 is equal to the period of the color subcarrier. FIG. 8 is a diagram of its operating waveforms. a is the clock (color subcarrier) of the counter 9 in Fig. 5;
b is a pulse with a width of one color subcarrier period generated by the logic circuit 10 or indicating the carry output of the counter 9, and c is a
d is the output obtained by ANDing b and Cf), e is a signal with a frequency three times that of the color subcarrier, and f is a signal with a desired 1-bit width. In FIG. terminal 8
The signals b appear at 00, e at 804, c at 805, d at the output of the AND circuit 801, and f at the output 803 of the flip-flop 802. As described above, the present invention provides a first means for obtaining a signal with a period of one frame by separating horizontal and vertical synchronizing signals from a video signal and comparing the phases of the two, and an odd number of color subcarriers of the video signal. a second means for obtaining a clock with double the frequency; a third means for obtaining a signal with a period of two frames by comparing the output of the first means and the phase of the color subcarrier; a fourth means for counting clocks; and a fifth means for controlling the fourth means so that a predetermined state of the fourth means and the output signal of the third means have a predetermined phase relationship. and a fifth means for generating various control signals in response to the state of the fourth means. Processing can be performed with the pixel synchronization signals completely synchronized.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a block diagram of a device to which the time adjustment device for different synchronized video signals of the present invention is applied, Fig. 2 is a waveform diagram for explaining the device, and Fig. 3 4 is a block diagram of a time adjustment device for different types of synchronized video signals according to an embodiment of the present invention; FIG.
1'M2n is a waveform diagram for explaining the same device, FIG. 5 is a block diagram of the video device in another embodiment, and FIG. A waveform diagram for explanation, FIG. 7 is a circuit diagram of a device for obtaining the same signal as the circuit shown in FIG. 3 from the circuit shown in FIG. 5, and FIG.
b, c, d, e, f are waveform diagrams for explaining the operation. 12...Color subcarrier input terminal, 13...
・Vertical synchronization signal input terminal, 14...Horizontal synchronization signal input terminal, 15...Clock input terminal, 1,
2... Monostable multivibrator, 3, 5, 8
...AND circuit, 4,6,7゜゜゜゛゜゜flip-flop, 9 ...Counter, 10 ...
・Logic circuit, 11...NOR circuit.

Claims (1)

[Claims] 1 Separate the horizontal and vertical synchronization signals from the composite video signal,
a first means for obtaining a signal with a period of one frame by comparing the phases of the two; a second means for obtaining a clock having a frequency that is an odd number multiple of the color subcarrier of the video signal; a third means for comparing the phase of the output and the color subcarrier to obtain a signal with a period of two frames; a fourth means for returning to an initial state when counting the clock or the color subcarrier; and a fourth means for returning to an initial state when counting the clock or the color subcarrier; 4; and a sixth means for generating various control signals in response to the state of the fourth means. .